Home
last modified time | relevance | path

Searched refs:i8 (Results 1 – 25 of 12652) sorted by relevance

12345678910>>...507

/external/llvm-project/llvm/test/CodeGen/SystemZ/Large/
Dbranch-01.ll7 target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64"
10 %0 = type { i8, i8, i16, i64, i32 }
11 %1 = type { [10 x i8] }
12 %2 = type { [15 x i8] }
13 %3 = type { i32, i8, i16, i32, %4 }
14 %4 = type { %1, [10 x i8] }
15 %5 = type <{ i16, i8, %2, %0, %6, %4, i16, i16 }>
17 %7 = type { [10 x i8] }
20 @.str.1 = external dso_local unnamed_addr constant [4 x i8], align 2
21 @.str.2 = external dso_local unnamed_addr constant [4 x i8], align 2
[all …]
/external/llvm-project/llvm/test/Transforms/InstCombine/X86/
Dx86-pshufb.ll6 define <16 x i8> @identity_test(<16 x i8> %InVec) {
8 ; CHECK-NEXT: ret <16 x i8> [[INVEC:%.*]]
10 …i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i…
11 ret <16 x i8> %1
14 define <32 x i8> @identity_test_avx2(<32 x i8> %InVec) {
16 ; CHECK-NEXT: ret <32 x i8> [[INVEC:%.*]]
18 …i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %InVec, <32 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, …
19 ret <32 x i8> %1
22 define <64 x i8> @identity_test_avx512(<64 x i8> %InVec) {
24 ; CHECK-NEXT: ret <64 x i8> [[INVEC:%.*]]
[all …]
/external/llvm-project/llvm/test/CodeGen/SystemZ/
Dloop-04.ll6 target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"
9 %0 = type <{ i64, [11 x i8] }>
11 …i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 }>, <{ i64, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 …
19 …i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 }>, <{ i64, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 …
20 %4 = bitcast [11 x i8]* %3 to i88*
Dvec-const-07.ll6 define <16 x i8> @f1() {
10 ret <16 x i8> <i8 1, i8 1, i8 1, i8 1,
11 i8 1, i8 1, i8 1, i8 1,
12 i8 1, i8 1, i8 1, i8 1,
13 i8 1, i8 1, i8 1, i8 1>
17 define <16 x i8> @f2() {
21 ret <16 x i8> <i8 201, i8 201, i8 201, i8 201,
22 i8 201, i8 201, i8 201, i8 201,
23 i8 201, i8 201, i8 201, i8 201,
24 i8 201, i8 201, i8 201, i8 201>
[all …]
Dvec-const-13.ll7 define <16 x i8> @f1() {
11 ret <16 x i8> <i8 0, i8 0, i8 128, i8 0,
12 i8 0, i8 0, i8 128, i8 0,
13 i8 0, i8 0, i8 128, i8 0,
14 i8 0, i8 0, i8 128, i8 0>
18 define <16 x i8> @f2() {
22 ret <16 x i8> <i8 0, i8 1, i8 255, i8 255,
23 i8 0, i8 1, i8 255, i8 255,
24 i8 0, i8 1, i8 255, i8 255,
25 i8 0, i8 1, i8 255, i8 255>
[all …]
Dint-uadd-12.ll9 … <{ i8, i64, { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i32, i8, i8, [2 x i…
18 …i8, i64, { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i32, i8, i8, [2 x i8], …
23 …i8, i64, { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i32, i8, i8, [2 x i8], …
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dstore-vector-pred.ll14 %v0 = load i8, i8* undef, align 1
15 %v1 = zext i8 %v0 to i32
20 …%v6 = call <128 x i8> @llvm.masked.load.v128i8.p0v128i8(<128 x i8>* nonnull undef, i32 1, <128 x i…
21 …i8> %v6, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4…
22 …i8> %v7, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1…
23 %v9 = zext <128 x i8> %v8 to <128 x i32>
34 %v20 = getelementptr inbounds i8, i8* null, i32 2160
35 %v21 = bitcast i8* %v20 to i32*
44 declare <128 x i8> @llvm.masked.load.v128i8.p0v128i8(<128 x i8>*, i32 immarg, <128 x i1>, <128 x i8…
Dswp-loop-carried-crash.ll9 %0 = type { %1*, [2 x [2 x %39]], [2 x [2 x %39]], [2 x i8], [2 x i8], [2 x i8], [2 x i8], i32, i32…
10 %1 = type { %0, %2, %3, %15, %16*, %98*, %99, %105*, %295*, %299, %303, %304, %304, %307, i8, i8, i…
11 %2 = type <{ %1*, i8, [3 x i8] }>
12 %3 = type { %1*, i8, i32, i8, %4*, %8, %307, %12*, [10 x i8*], [10 x i8], %307 }
17 %8 = type { %9, %4*, [16 x i32], void (%8*, i8*, i32)*, i8*, %307, %307 }
18 %9 = type { [16 x %11], i16, i8, %10*, %11 }
19 %10 = type { i64, [8 x i8] }
24 %15 = type <{ %1*, i8, [3 x i8] }>
25 … i8, i16, i16, i8, %17, i32, %22, %27, [4 x i8], [6 x [512 x %28]], %94, [6 x %29], [6 x i8*], %94…
26 %17 = type { %18*, %21, %21, i32, i8 }
[all …]
/external/llvm/test/Transforms/InstCombine/
Dx86-pshufb.ll6 define <16 x i8> @identity_test(<16 x i8> %InVec) {
8 ; CHECK-NEXT: ret <16 x i8> %InVec
10 …i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i…
11 ret <16 x i8> %1
14 define <32 x i8> @identity_test_avx2(<32 x i8> %InVec) {
16 ; CHECK-NEXT: ret <32 x i8> %InVec
18 …i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %InVec, <32 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, …
19 ret <32 x i8> %1
24 define <16 x i8> @fold_to_zero_vector(<16 x i8> %InVec) {
26 ; CHECK-NEXT: ret <16 x i8> zeroinitializer
[all …]
D2006-12-23-Select-Cmp-Cmp.ll9 …i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8, i32, i32, i32, i8, i32, i32, i32, i32, i16, …
10 %struct.mng_palette8e = type { i8, i8, i8 }
11 %struct.mng_pushdata = type { i8*, i8*, i32, i8, i8*, i32 }
12 …i8, i8, i8, i8, i8, i8, i8, i16, i16, i16, i8, i16, i8, i8, i32, i32, i8, i32, i32, i32, i32, i32,…
13 …struct.z_stream = type { i8*, i32, i32, i8*, i32, i32, i8*, %struct.internal_state*, i8* (i8*, i32…
17 %tmp = load i8, i8* null ; <i8> [#uses=1]
18 %tmp.upgrd.1 = icmp ugt i8 %tmp, 8 ; <i1> [#uses=1]
/external/llvm-project/llvm/test/CodeGen/X86/
Dvector-shuffle-combining-avx512vbmi.ll5 declare <16 x i8> @llvm.x86.avx512.mask.vpermi2var.qi.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)
6 declare <16 x i8> @llvm.x86.avx512.mask.vpermt2var.qi.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)
7 declare <16 x i8> @llvm.x86.avx512.maskz.vpermt2var.qi.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)
9 declare <32 x i8> @llvm.x86.avx512.mask.vpermi2var.qi.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)
10 declare <32 x i8> @llvm.x86.avx512.mask.vpermt2var.qi.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)
11 declare <32 x i8> @llvm.x86.avx512.maskz.vpermt2var.qi.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)
13 declare <64 x i8> @llvm.x86.avx512.mask.vpermi2var.qi.512(<64 x i8>, <64 x i8>, <64 x i8>, i64)
14 declare <64 x i8> @llvm.x86.avx512.mask.vpermt2var.qi.512(<64 x i8>, <64 x i8>, <64 x i8>, i64)
15 declare <64 x i8> @llvm.x86.avx512.maskz.vpermt2var.qi.512(<64 x i8>, <64 x i8>, <64 x i8>, i64)
17 declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>)
[all …]
Dvector-shuffle-combining-avx2.ll9 declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>)
10 declare <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8>, <32 x i8>)
12 define <32 x i8> @combine_pshufb_pslldq(<32 x i8> %a0) {
17 …i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %a0, <32 x i8> <i8 128, i8 128, i8 128, i8 128, i8 128, i8 12…
18 …%2 = shufflevector <32 x i8> %1, <32 x i8> zeroinitializer, <32 x i32> <i32 32, i32 32, i32 32, i3…
19 ret <32 x i8> %2
22 define <32 x i8> @combine_pshufb_psrldq(<32 x i8> %a0) {
27 …i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %a0, <32 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14…
28 …%2 = shufflevector <32 x i8> %1, <32 x i8> zeroinitializer, <32 x i32> <i32 8, i32 9, i32 10, i32 …
29 ret <32 x i8> %2
[all …]
Dvector-shuffle-combining-ssse3.ll10 declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>)
12 define <16 x i8> @combine_vpshufb_as_zero(<16 x i8> %a0) {
22 …i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 128, i8 0, i8 0, i8 0, i8 0, i8 0, i8…
23 …i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %res0, <16 x i8> <i8 0, i8 128, i8 0, i8 0, i8 0, i8 0, …
24 …i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %res1, <16 x i8> <i8 0, i8 1, i8 128, i8 128, i8 128, i8…
25 ret <16 x i8> %res2
28 define <16 x i8> @combine_vpshufb_as_movq(<16 x i8> %a0) {
38 …i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 0, i8 128, i8 1, i8 128, i8 2, i8 128…
39 …i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %res0, <16 x i8> <i8 0, i8 2, i8 4, i8 6, i8 8, i8 10, i…
40 ret <16 x i8> %res1
[all …]
/external/llvm/test/CodeGen/SystemZ/
Dvec-const-07.ll6 define <16 x i8> @f1() {
10 ret <16 x i8> <i8 1, i8 1, i8 1, i8 1,
11 i8 1, i8 1, i8 1, i8 1,
12 i8 1, i8 1, i8 1, i8 1,
13 i8 1, i8 1, i8 1, i8 1>
17 define <16 x i8> @f2() {
21 ret <16 x i8> <i8 201, i8 201, i8 201, i8 201,
22 i8 201, i8 201, i8 201, i8 201,
23 i8 201, i8 201, i8 201, i8 201,
24 i8 201, i8 201, i8 201, i8 201>
[all …]
Dvec-const-13.ll7 define <16 x i8> @f1() {
11 ret <16 x i8> <i8 0, i8 0, i8 128, i8 0,
12 i8 0, i8 0, i8 128, i8 0,
13 i8 0, i8 0, i8 128, i8 0,
14 i8 0, i8 0, i8 128, i8 0>
18 define <16 x i8> @f2() {
22 ret <16 x i8> <i8 0, i8 1, i8 255, i8 255,
23 i8 0, i8 1, i8 255, i8 255,
24 i8 0, i8 1, i8 255, i8 255,
25 i8 0, i8 1, i8 255, i8 255>
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/msa/
Di8.ll6 …di_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i…
7 …_andi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0,…
11 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_andi_b_ARG1
12 %1 = tail call <16 x i8> @llvm.mips.andi.b(<16 x i8> %0, i32 25)
13 store <16 x i8> %1, <16 x i8>* @llvm_mips_andi_b_RES
17 declare <16 x i8> @llvm.mips.andi.b(<16 x i8>, i32) nounwind
25 …bmnzi_b_ARG1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0,…
26 …zi_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i…
27 …bmnzi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0,…
31 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bmnzi_b_ARG1
[all …]
/external/llvm/test/CodeGen/Mips/msa/
Di8.ll6 …di_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i…
7 …_andi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0,…
11 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_andi_b_ARG1
12 %1 = tail call <16 x i8> @llvm.mips.andi.b(<16 x i8> %0, i32 25)
13 store <16 x i8> %1, <16 x i8>* @llvm_mips_andi_b_RES
17 declare <16 x i8> @llvm.mips.andi.b(<16 x i8>, i32) nounwind
25 …bmnzi_b_ARG1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0,…
26 …zi_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i…
27 …bmnzi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0,…
31 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bmnzi_b_ARG1
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-sli-sri-opt.ll3 define void @testLeftGood(<16 x i8> %src1, <16 x i8> %src2, <16 x i8>* %dest) nounwind {
6 …nd <16 x i8> %src1, <i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 25…
7 …%vshl_n = shl <16 x i8> %src2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, …
8 %result = or <16 x i8> %and.i, %vshl_n
9 store <16 x i8> %result, <16 x i8>* %dest, align 16
13 define void @testLeftBad(<16 x i8> %src1, <16 x i8> %src2, <16 x i8>* %dest) nounwind {
16 …nd <16 x i8> %src1, <i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 16…
17 …%vshl_n = shl <16 x i8> %src2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, …
18 %result = or <16 x i8> %and.i, %vshl_n
19 store <16 x i8> %result, <16 x i8>* %dest, align 16
[all …]
/external/llvm-project/llvm/test/Transforms/InstSimplify/
Dmaxmin_intrinsics.ll7 declare i8 @llvm.smax.i8(i8, i8)
8 declare <2 x i8> @llvm.smax.v2i8(<2 x i8>, <2 x i8>)
10 declare i8 @llvm.smin.i8(i8, i8)
11 declare <2 x i8> @llvm.smin.v2i8(<2 x i8>, <2 x i8>)
12 declare i8 @llvm.umax.i8(i8, i8)
13 declare <2 x i8> @llvm.umax.v2i8(<2 x i8>, <2 x i8>)
14 declare i8 @llvm.umin.i8(i8, i8)
15 declare <2 x i8> @llvm.umin.v2i8(<2 x i8>, <2 x i8>)
34 define <2 x i8> @umax_sameval(<2 x i8> %x) {
36 ; CHECK-NEXT: ret <2 x i8> [[X:%.*]]
[all …]
/external/llvm-project/llvm/test/Transforms/InstSimplify/ConstProp/
Dsaturating-add-sub.ll4 declare i8 @llvm.uadd.sat.i8(i8, i8)
5 declare i8 @llvm.sadd.sat.i8(i8, i8)
6 declare <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8>, <2 x i8>)
7 declare <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8>, <2 x i8>)
9 declare i8 @llvm.usub.sat.i8(i8, i8)
10 declare i8 @llvm.ssub.sat.i8(i8, i8)
11 declare <2 x i8> @llvm.usub.sat.v2i8(<2 x i8>, <2 x i8>)
12 declare <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8>, <2 x i8>)
14 define i8 @test_uadd_scalar_no_sat() {
16 ; CHECK-NEXT: ret i8 30
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/
Ddagcombine-store-gep-chain-slow.ll7 declare i8 @k(i8*)
12 %old_val = alloca i8, align 1
13 %new_val = alloca i8, align 1
14 %simd = alloca i8, align 1
15 %code = alloca [269 x i8], align 1
17 %call = call zeroext i8 @k(i8* %simd)
18 store i8 %call, i8* %simd, align 1
20 %arrayinit.begin = getelementptr inbounds [269 x i8], [269 x i8]* %code, i32 0, i32 0
21 store i8 32, i8* %arrayinit.begin, align 1
22 %arrayinit.element = getelementptr inbounds i8, i8* %arrayinit.begin, i32 1
[all …]
/external/llvm/test/CodeGen/X86/
Dbyval5.ll27 %struct.s = type { i8, i8, i8, i8, i8, i8, i8, i8,
28 i8, i8, i8, i8, i8, i8, i8, i8,
29 i8, i8, i8, i8, i8, i8, i8, i8,
30 i8, i8, i8, i8, i8, i8, i8, i8,
31 i8, i8, i8, i8, i8, i8, i8, i8,
32 i8, i8, i8, i8, i8, i8, i8, i8,
33 i8, i8, i8, i8, i8, i8, i8, i8,
34 i8, i8, i8, i8, i8, i8, i8, i8,
35 i8, i8, i8, i8, i8, i8, i8, i8,
36 i8, i8, i8, i8, i8, i8, i8, i8,
[all …]
Dvector-shuffle-combining-avx2.ll6 declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>)
7 declare <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8>, <32 x i8>)
9 define <32 x i8> @combine_pshufb_pslldq(<32 x i8> %a0) {
14 …i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %a0, <32 x i8> <i8 128, i8 128, i8 128, i8 128, i8 128, i8 12…
15 …%2 = shufflevector <32 x i8> %1, <32 x i8> zeroinitializer, <32 x i32> <i32 32, i32 32, i32 32, i3…
16 ret <32 x i8> %2
19 define <32 x i8> @combine_pshufb_psrldq(<32 x i8> %a0) {
24 …i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %a0, <32 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14…
25 …%2 = shufflevector <32 x i8> %1, <32 x i8> zeroinitializer, <32 x i32> <i32 8, i32 9, i32 10, i32 …
26 ret <32 x i8> %2
[all …]
/external/llvm-project/llvm/test/Transforms/InstCombine/
D2006-12-23-Select-Cmp-Cmp.ll9 …i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8, i32, i32, i32, i8, i32, i32, i32, i32, i16, …
10 %struct.mng_palette8e = type { i8, i8, i8 }
11 %struct.mng_pushdata = type { i8*, i8*, i32, i8, i8*, i32 }
12 …i8, i8, i8, i8, i8, i8, i8, i16, i16, i16, i8, i16, i8, i8, i32, i32, i8, i32, i32, i32, i32, i32,…
13 …struct.z_stream = type { i8*, i32, i32, i8*, i32, i32, i8*, %struct.internal_state*, i8* (i8*, i32…
17 %tmp = load i8, i8* null ; <i8> [#uses=1]
18 %tmp.upgrd.1 = icmp ugt i8 %tmp, 8 ; <i1> [#uses=1]
/external/llvm-project/llvm/test/Analysis/CostModel/X86/
Drem.ll28 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = srem i8 undef, undef
29 ; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %V16i8 = srem <16 x i8> …
30 ; CHECK-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %V32i8 = srem <32 x i8> …
31 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %V64i8 = srem <64 x i8>…
49 %I8 = srem i8 undef, undef
50 %V16i8 = srem <16 x i8> undef, undef
51 %V32i8 = srem <32 x i8> undef, undef
52 %V64i8 = srem <64 x i8> undef, undef
71 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = urem i8 undef, undef
72 ; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %V16i8 = urem <16 x i8> …
[all …]

12345678910>>...507