| /external/llvm-project/llvm/lib/Target/AVR/ |
| D | AVRExpandPseudoInsts.cpp | 148 bool DstIsKill = MI.getOperand(1).isKill(); in expandArith()
149 bool SrcIsKill = MI.getOperand(2).isKill(); in expandArith()
181 bool DstIsKill = MI.getOperand(1).isKill(); in expandLogic()
182 bool SrcIsKill = MI.getOperand(2).isKill(); in expandLogic()
227 bool SrcIsKill = MI.getOperand(1).isKill(); in expandLogicImm()
279 bool SrcIsKill = MI.getOperand(1).isKill(); in expand()
331 bool SrcIsKill = MI.getOperand(1).isKill(); in expand()
394 bool DstIsKill = MI.getOperand(1).isKill(); in expand()
424 bool DstIsKill = MI.getOperand(1).isKill(); in expand()
462 bool DstIsKill = MI.getOperand(0).isKill(); in expand()
[all …]
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| D | AVRRelaxMemOperations.cpp | 112 .addReg(Src.getReg(), getKillRegState(Src.isKill())); in relax()
116 .addReg(Ptr.getReg(), getKillRegState(Ptr.isKill())); in relax()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRExpandPseudoInsts.cpp | 148 bool DstIsKill = MI.getOperand(1).isKill(); in expandArith()
149 bool SrcIsKill = MI.getOperand(2).isKill(); in expandArith()
181 bool DstIsKill = MI.getOperand(1).isKill(); in expandLogic()
182 bool SrcIsKill = MI.getOperand(2).isKill(); in expandLogic()
227 bool SrcIsKill = MI.getOperand(1).isKill(); in expandLogicImm()
279 bool SrcIsKill = MI.getOperand(1).isKill(); in expand()
331 bool SrcIsKill = MI.getOperand(1).isKill(); in expand()
394 bool DstIsKill = MI.getOperand(1).isKill(); in expand()
424 bool DstIsKill = MI.getOperand(0).isKill(); in expand()
425 bool SrcIsKill = MI.getOperand(1).isKill(); in expand()
[all …]
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| D | AVRRelaxMemOperations.cpp | 112 .addReg(Src.getReg(), getKillRegState(Src.isKill())); in relax()
116 .addReg(Ptr.getReg(), getKillRegState(Ptr.isKill())); in relax()
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| /external/llvm/lib/CodeGen/ |
| D | TwoAddressInstructionPass.cpp | 238 if (!UseMO.isKill()) in sink3AddrInstruction()
280 if (MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS))) { in sink3AddrInstruction()
880 if (MOReg != Reg && (MO.isKill() || in rescheduleMIBelowKill()
929 bool isKill = in rescheduleMIBelowKill() local
930 MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS)); in rescheduleMIBelowKill()
932 ((isKill && Uses.count(MOReg)) || Kills.count(MOReg))) in rescheduleMIBelowKill()
935 if (MOReg == Reg && !isKill) in rescheduleMIBelowKill()
1058 bool isKill = MO.isKill() || (LIS && isPlainlyKilled(KillMI, MOReg, LIS)); in rescheduleKillAboveMI() local
1059 if (MOReg == Reg && !isKill) in rescheduleKillAboveMI()
1062 if (isKill && MOReg != Reg) in rescheduleKillAboveMI()
[all …]
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| D | MachineInstrBundle.cpp | 152 if (MO.isKill()) in finalizeBundle()
161 if (MO.isKill()) in finalizeBundle()
211 bool isKill = KilledUseSet.count(Reg); in finalizeBundle() local
213 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) | in finalizeBundle()
324 if (MO.isKill()) in analyzePhysReg()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TwoAddressInstructionPass.cpp | 266 if (!UseMO.isKill()) in sink3AddrInstruction()
308 if (MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS))) { in sink3AddrInstruction()
920 if (MOReg != Reg && (MO.isKill() || in rescheduleMIBelowKill()
972 bool isKill = in rescheduleMIBelowKill() local
973 MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS)); in rescheduleMIBelowKill()
974 if (MOReg != Reg && ((isKill && regOverlapsSet(Uses, MOReg, TRI)) || in rescheduleMIBelowKill()
978 if (MOReg == Reg && !isKill) in rescheduleMIBelowKill()
1101 bool isKill = MO.isKill() || (LIS && isPlainlyKilled(KillMI, MOReg, LIS)); in rescheduleKillAboveMI() local
1102 if (MOReg == Reg && !isKill) in rescheduleKillAboveMI()
1105 if (isKill && MOReg != Reg) in rescheduleKillAboveMI()
[all …]
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| D | MachineInstrBundle.cpp | 164 if (MO.isKill()) in finalizeBundle()
173 if (MO.isKill()) in finalizeBundle()
223 bool isKill = KilledUseSet.count(Reg); in finalizeBundle() local
225 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) | in finalizeBundle()
341 if (MO.isKill()) in AnalyzePhysRegInBundle()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCVSXFMAMutate.cpp | 191 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill() in processBlock()
195 } else if (LIS->getInterval(Reg3).Query(FMAIdx).isKill() in processBlock()
224 bool AddRegKill = AddendMI->getOperand(1).isKill(); in processBlock()
225 bool KilledProdRegKill = MI->getOperand(KilledProdOp).isKill(); in processBlock()
226 bool OtherProdRegKill = MI->getOperand(OtherProdOp).isKill(); in processBlock()
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| D | PPCInstrInfo.cpp | 353 bool Reg1IsKill = MI.getOperand(1).isKill(); in commuteInstructionImpl()
354 bool Reg2IsKill = MI.getOperand(2).isKill(); in commuteInstructionImpl()
957 unsigned SrcReg, bool isKill, in StoreRegToStackSlot() argument
970 getKillRegState(isKill)), in StoreRegToStackSlot()
976 getKillRegState(isKill)), in StoreRegToStackSlot()
981 getKillRegState(isKill)), in StoreRegToStackSlot()
986 getKillRegState(isKill)), in StoreRegToStackSlot()
991 getKillRegState(isKill)), in StoreRegToStackSlot()
997 getKillRegState(isKill)), in StoreRegToStackSlot()
1003 getKillRegState(isKill)), in StoreRegToStackSlot()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCVSXFMAMutate.cpp | 192 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill() in processBlock()
196 } else if (LIS->getInterval(Reg3).Query(FMAIdx).isKill() in processBlock()
225 bool AddRegKill = AddendMI->getOperand(1).isKill(); in processBlock()
226 bool KilledProdRegKill = MI.getOperand(KilledProdOp).isKill(); in processBlock()
227 bool OtherProdRegKill = MI.getOperand(OtherProdOp).isKill(); in processBlock()
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| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCVSXFMAMutate.cpp | 192 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill() in processBlock()
196 } else if (LIS->getInterval(Reg3).Query(FMAIdx).isKill() in processBlock()
225 bool AddRegKill = AddendMI->getOperand(1).isKill(); in processBlock()
226 bool KilledProdRegKill = MI.getOperand(KilledProdOp).isKill(); in processBlock()
227 bool OtherProdRegKill = MI.getOperand(OtherProdOp).isKill(); in processBlock()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.h | 99 unsigned SrcReg, bool isKill, int FrameIndex, in storeRegToStackSlot() argument
102 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0); in storeRegToStackSlot()
115 unsigned SrcReg, bool isKill, int FrameIndex,
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | TwoAddressInstructionPass.cpp | 780 if (MOReg != Reg && (MO.isKill() || in rescheduleMIBelowKill()
832 bool isKill = in rescheduleMIBelowKill() local
833 MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS)); in rescheduleMIBelowKill()
834 if (MOReg != Reg && ((isKill && regOverlapsSet(Uses, MOReg, TRI)) || in rescheduleMIBelowKill()
838 if (MOReg == Reg && !isKill) in rescheduleMIBelowKill()
960 bool isKill = MO.isKill() || (LIS && isPlainlyKilled(KillMI, MOReg, LIS)); in rescheduleKillAboveMI() local
961 if (MOReg == Reg && !isKill) in rescheduleKillAboveMI()
964 if (isKill && MOReg != Reg) in rescheduleKillAboveMI()
1003 !(MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS)))) in rescheduleKillAboveMI()
1249 if (NewMIs[1]->getOperand(NewSrcIdx).isKill()) { in tryInstructionTransform()
[all …]
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| D | MachineInstrBundle.cpp | 164 if (MO.isKill()) in finalizeBundle()
173 if (MO.isKill()) in finalizeBundle()
223 bool isKill = KilledUseSet.count(Reg); in finalizeBundle() local
225 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) | in finalizeBundle()
340 if (MO.isKill()) in AnalyzePhysRegInBundle()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.h | 114 unsigned SrcReg, bool isKill, int FrameIndex, in storeRegToStackSlot() argument
117 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0); in storeRegToStackSlot()
130 unsigned SrcReg, bool isKill, int FrameIndex,
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.h | 118 Register SrcReg, bool isKill, int FrameIndex, in storeRegToStackSlot() argument
121 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0); in storeRegToStackSlot()
134 Register SrcReg, bool isKill, int FrameIndex,
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| /external/llvm-project/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.cpp | 396 Register SrcReg, bool isKill, int FI, in storeRegToStackSlot() argument
411 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
414 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
417 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
420 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
423 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
428 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.cpp | 396 unsigned SrcReg, bool isKill, int FI, in storeRegToStackSlot() argument
411 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
414 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
417 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
420 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
423 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
428 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.cpp | 393 unsigned SrcReg, bool isKill, int FI, in storeRegToStackSlot() argument
408 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
411 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
414 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
417 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
420 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
425 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonNewValueJump.cpp | 530 if (MI.getOperand(1).isKill()) in runOnMachineFunction()
535 if (MI.getOperand(2).isKill()) in runOnMachineFunction()
615 localMO.isKill() && feederReg == localMO.getReg()) { in runOnMachineFunction()
670 cmpInstr->getOperand(0).isKill()) in runOnMachineFunction()
673 cmpInstr->getOperand(1).isKill()) in runOnMachineFunction()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineOperand.h | 297 bool isKill() const { in isKill() function
581 bool isKill = false, bool isDead = false,
607 bool isKill = false, bool isDead = false,
614 assert(!(isKill && isDef) && "Kill flag on def");
618 Op.IsKill = isKill;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.cpp | 77 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPImmInst()
113 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPConstInst()
147 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPImmInst()
190 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPConstInst()
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| /external/llvm-project/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.cpp | 77 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPImmInst()
113 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPConstInst()
147 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPImmInst()
190 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPConstInst()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.cpp | 78 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPImmInst()
114 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPConstInst()
148 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPImmInst()
191 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPConstInst()
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