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Searched refs:midr (Results 1 – 25 of 104) sorted by relevance

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/external/cpuinfo/src/arm/
Dmidr.h39 inline static uint32_t midr_set_implementer(uint32_t midr, uint32_t implementer) { in midr_set_implementer() argument
40 return (midr & ~CPUINFO_ARM_MIDR_IMPLEMENTER_MASK) | in midr_set_implementer()
44 inline static uint32_t midr_set_variant(uint32_t midr, uint32_t variant) { in midr_set_variant() argument
45 return (midr & ~CPUINFO_ARM_MIDR_VARIANT_MASK) | in midr_set_variant()
49 inline static uint32_t midr_set_architecture(uint32_t midr, uint32_t architecture) { in midr_set_architecture() argument
50 return (midr & ~CPUINFO_ARM_MIDR_ARCHITECTURE_MASK) | in midr_set_architecture()
54 inline static uint32_t midr_set_part(uint32_t midr, uint32_t part) { in midr_set_part() argument
55 return (midr & ~CPUINFO_ARM_MIDR_PART_MASK) | in midr_set_part()
59 inline static uint32_t midr_set_revision(uint32_t midr, uint32_t revision) { in midr_set_revision() argument
60 return (midr & ~CPUINFO_ARM_MIDR_REVISION_MASK) | in midr_set_revision()
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Duarch.c9 uint32_t midr, in cpuinfo_arm_decode_vendor_uarch() argument
16 switch (midr_get_implementer(midr)) { in cpuinfo_arm_decode_vendor_uarch()
19 switch (midr_get_part(midr)) { in cpuinfo_arm_decode_vendor_uarch()
62 *uarch = (midr & CPUINFO_ARM_MIDR_VARIANT_MASK) == 0 ? in cpuinfo_arm_decode_vendor_uarch()
106 switch (midr_get_part(midr) >> 8) { in cpuinfo_arm_decode_vendor_uarch()
119 cpuinfo_log_warning("unknown ARM CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); in cpuinfo_arm_decode_vendor_uarch()
125 switch (midr_get_part(midr)) { in cpuinfo_arm_decode_vendor_uarch()
140 cpuinfo_log_warning("unknown Broadcom CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); in cpuinfo_arm_decode_vendor_uarch()
146 switch (midr_get_part(midr)) { in cpuinfo_arm_decode_vendor_uarch()
157 cpuinfo_log_warning("unknown Cavium CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); in cpuinfo_arm_decode_vendor_uarch()
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Dapi.h89 uint32_t midr,
99 uint32_t midr,
114 uint32_t midr,
Dcache.c13 uint32_t midr, in cpuinfo_arm_decode_cache() argument
25 switch (midr_get_part(midr) >> 8) { in cpuinfo_arm_decode_cache()
514 if (midr_is_qualcomm_cortex_a53_silver(midr)) { in cpuinfo_arm_decode_cache()
710 if (midr_is_qualcomm_cortex_a55_silver(midr)) { in cpuinfo_arm_decode_cache()
1023 switch (midr) { in cpuinfo_arm_decode_cache()
1327 if (midr_is_kryo_silver(midr)) { in cpuinfo_arm_decode_cache()
/external/cpuinfo/src/arm/linux/
Dclusters.c199 …if ((cluster_midr & CPUINFO_ARM_MIDR_IMPLEMENTER_MASK) != (processors[i].midr & CPUINFO_ARM_MIDR_I… in cpuinfo_arm_linux_detect_core_clusters_by_heuristic()
203 i, midr_get_implementer(processors[i].midr), midr_get_implementer(cluster_midr)); in cpuinfo_arm_linux_detect_core_clusters_by_heuristic()
207 cluster_midr = midr_copy_implementer(cluster_midr, processors[i].midr); in cpuinfo_arm_linux_detect_core_clusters_by_heuristic()
214 …if ((cluster_midr & CPUINFO_ARM_MIDR_VARIANT_MASK) != (processors[i].midr & CPUINFO_ARM_MIDR_VARIA… in cpuinfo_arm_linux_detect_core_clusters_by_heuristic()
218 i, midr_get_variant(processors[i].midr), midr_get_variant(cluster_midr)); in cpuinfo_arm_linux_detect_core_clusters_by_heuristic()
222 cluster_midr = midr_copy_variant(cluster_midr, processors[i].midr); in cpuinfo_arm_linux_detect_core_clusters_by_heuristic()
229 …if ((cluster_midr & CPUINFO_ARM_MIDR_PART_MASK) != (processors[i].midr & CPUINFO_ARM_MIDR_PART_MAS… in cpuinfo_arm_linux_detect_core_clusters_by_heuristic()
233 i, midr_get_part(processors[i].midr), midr_get_part(cluster_midr)); in cpuinfo_arm_linux_detect_core_clusters_by_heuristic()
237 cluster_midr = midr_copy_part(cluster_midr, processors[i].midr); in cpuinfo_arm_linux_detect_core_clusters_by_heuristic()
244 …if ((cluster_midr & CPUINFO_ARM_MIDR_REVISION_MASK) != (processors[i].midr & CPUINFO_ARM_MIDR_REVI… in cpuinfo_arm_linux_detect_core_clusters_by_heuristic()
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Dmidr.c556 … if ((processors[cluster_leader].midr ^ cluster_configs[c].cluster_midr[cluster]) & midr_mask) { in cpuinfo_arm_linux_detect_cluster_midr_by_chipset()
558 processors[cluster_leader].midr, cluster_configs[c].cluster_midr[cluster]); in cpuinfo_arm_linux_detect_cluster_midr_by_chipset()
567 processors[cluster_leader].midr = cluster_configs[c].cluster_midr[cluster]; in cpuinfo_arm_linux_detect_cluster_midr_by_chipset()
616 const uint32_t big_midr = processors[processors[last_processor_with_midr].package_leader_id].midr; in cpuinfo_arm_linux_detect_cluster_midr_by_big_little_heuristic()
650 const uint32_t midr = (cluster_leader == little_cluster_leader) ? little_midr : big_midr; in cpuinfo_arm_linux_detect_cluster_midr_by_big_little_heuristic() local
651 if ((processors[cluster_leader].midr ^ midr) & midr_mask) { in cpuinfo_arm_linux_detect_cluster_midr_by_big_little_heuristic()
654 processors[cluster_leader].midr, cluster_leader, midr); in cpuinfo_arm_linux_detect_cluster_midr_by_big_little_heuristic()
667 const uint32_t midr = (cluster_leader == little_cluster_leader) ? little_midr : big_midr; in cpuinfo_arm_linux_detect_cluster_midr_by_big_little_heuristic() local
668 cpuinfo_log_info("assume processor %"PRIu32" to have MIDR %08"PRIx32, cluster_leader, midr); in cpuinfo_arm_linux_detect_cluster_midr_by_big_little_heuristic()
670 processors[cluster_leader].midr = midr; in cpuinfo_arm_linux_detect_cluster_midr_by_big_little_heuristic()
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Daarch32-isa.c30 uint32_t midr, in cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo() argument
72 switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { in cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo()
96 switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { in cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo()
108 isa->dot = !!(midr_get_variant(midr) >= 1); in cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo()
111 isa->dot = !!(midr_get_variant(midr) >= 2); in cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo()
121 if (architecture_version == 7 && midr_is_arm11(midr)) { in cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo()
154 switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { in cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo()
192 if (architecture_version >= 7 || midr_is_arm1156(midr)) { in cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo()
204 …tures & CPUINFO_ARM_LINUX_FEATURE_IDIV) == CPUINFO_ARM_LINUX_FEATURE_IDIV || midr_is_krait(midr)) { in cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo()
243 …features & CPUINFO_ARM_LINUX_FEATURE_VFPV4) || midr_is_cortex_a9(midr) || midr_is_scorpion(midr)) { in cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo()
Daarch64-isa.c10 uint32_t midr, in cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo() argument
50 switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { in cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo()
86 switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { in cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo()
101 isa->dot = !!(midr_get_variant(midr) >= 1); in cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo()
104 isa->dot = !!(midr_get_variant(midr) >= 2); in cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo()
Dapi.h175 uint32_t midr; member
242 if (processor_i->midr == processor_j->midr) { in cpuinfo_arm_linux_processor_equals()
243 if (midr_is_cortex_a53(processor_i->midr)) { in cpuinfo_arm_linux_processor_equals()
274 if (processor_i->midr != processor_j->midr) { in cpuinfo_arm_linux_processor_not_equals()
299 uint32_t midr,
312 uint32_t midr,
Dinit.c74 const uint32_t midr_a = processor_a->midr; in cmp_arm_linux_processor()
75 const uint32_t midr_b = processor_b->midr; in cmp_arm_linux_processor()
191 i, arm_linux_processors[i].midr); in cpuinfo_arm_linux_init()
213 last_midr = arm_linux_processors[i].midr; in cpuinfo_arm_linux_init()
371 arm_linux_processors[cluster_leader].midr, in cpuinfo_arm_linux_init()
381 arm_linux_processors[i].midr = arm_linux_processors[cluster_leader].midr; in cpuinfo_arm_linux_init()
392 i, arm_linux_processors[i].midr, arm_linux_processors[i].max_frequency); in cpuinfo_arm_linux_init()
402 …i, arm_linux_processors[i].system_processor_id, arm_linux_processors[i].midr, arm_linux_processors… in cpuinfo_arm_linux_init()
501 .midr = arm_linux_processors[i].midr, in cpuinfo_arm_linux_init()
526 .midr = arm_linux_processors[i].midr, in cpuinfo_arm_linux_init()
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Dcpuinfo.c320 processor->midr = midr_set_architecture(processor->midr, UINT32_C(0xF)); in parse_cpu_architecture()
396 processor->midr = midr_set_architecture(processor->midr, midr_architecture); in parse_cpu_architecture()
445 processor->midr = midr_set_part(processor->midr, cpu_part); in parse_cpu_part()
499 processor->midr = midr_set_implementer(processor->midr, cpu_implementer); in parse_cpu_implementer()
543 processor->midr = midr_set_variant(processor->midr, cpu_variant); in parse_cpu_variant()
567 processor->midr = midr_set_revision(processor->midr, cpu_revision); in parse_cpu_revision()
/external/arm-trusted-firmware/lib/cpus/aarch64/
Dcpuamu.c22 unsigned int midr, midr_mask; in midr_match() local
24 midr = (unsigned int)read_midr(); in midr_match()
27 return ((midr & midr_mask) == (cpu_midr & midr_mask)); in midr_match()
/external/arm-trusted-firmware/plat/nvidia/tegra/include/drivers/
Dflowctrl.h87 void tegra_fc_cluster_idle(uint32_t midr);
89 void tegra_fc_cluster_powerdn(uint32_t midr);
96 void tegra_fc_soc_powerdn(uint32_t midr);
/external/tensorflow/third_party/cpuinfo/
Dcpuinfo.patch80 diff --git a/src/arm/midr.h b/src/arm/midr.h
82 --- a/src/arm/midr.h
83 +++ b/src/arm/midr.h
84 @@ -183,6 +183,7 @@ inline static uint32_t midr_score_core(uint32_t midr) {
/external/arm-trusted-firmware/plat/hisilicon/hikey/
Dhikey_bl2_setup.c224 u_register_t midr; in hikey_boardid_init() local
226 midr = read_midr(); in hikey_boardid_init()
227 mmio_write_32(MEMORY_AXI_CHIP_ADDR, midr); in hikey_boardid_init()
229 (unsigned int)midr); in hikey_boardid_init()
/external/cpuinfo/test/mock/
Dmeizu-pro-7-plus.cc210 TEST(CORES, midr) { in TEST() argument
215 ASSERT_EQ(UINT32_C(0x410FD092), cpuinfo_get_core(i)->midr); in TEST()
221 ASSERT_EQ(UINT32_C(0x410FD034), cpuinfo_get_core(i)->midr); in TEST()
227 ASSERT_EQ(UINT32_C(0x410FD041), cpuinfo_get_core(i)->midr); in TEST()
362 TEST(CLUSTERS, midr) { in TEST() argument
366 ASSERT_EQ(UINT32_C(0x410FD092), cpuinfo_get_cluster(i)->midr); in TEST()
369 ASSERT_EQ(UINT32_C(0x410FD034), cpuinfo_get_cluster(i)->midr); in TEST()
372 ASSERT_EQ(UINT32_C(0x410FD041), cpuinfo_get_cluster(i)->midr); in TEST()
Dgalaxy-c9-pro.cc190 TEST(CORES, midr) { in TEST() argument
197 ASSERT_EQ(UINT32_C(0x410FD080), cpuinfo_get_core(i)->midr); in TEST()
203 ASSERT_EQ(UINT32_C(0x410FD034), cpuinfo_get_core(i)->midr); in TEST()
305 TEST(CLUSTERS, midr) { in TEST() argument
309 ASSERT_EQ(UINT32_C(0x410FD080), cpuinfo_get_cluster(i)->midr); in TEST()
312 ASSERT_EQ(UINT32_C(0x410FD034), cpuinfo_get_cluster(i)->midr); in TEST()
Dgalaxy-s6.cc190 TEST(CORES, midr) { in TEST() argument
197 ASSERT_EQ(UINT32_C(0x411FD070), cpuinfo_get_core(i)->midr); in TEST()
203 ASSERT_EQ(UINT32_C(0x410FD032), cpuinfo_get_core(i)->midr); in TEST()
305 TEST(CLUSTERS, midr) { in TEST() argument
309 ASSERT_EQ(UINT32_C(0x411FD070), cpuinfo_get_cluster(i)->midr); in TEST()
312 ASSERT_EQ(UINT32_C(0x410FD032), cpuinfo_get_cluster(i)->midr); in TEST()
Dlenovo-vibe-x2.cc171 TEST(CORES, midr) { in TEST() argument
178 ASSERT_EQ(UINT32_C(0x410FC0E0), cpuinfo_get_core(i)->midr); in TEST()
184 ASSERT_EQ(UINT32_C(0x410FC075), cpuinfo_get_core(i)->midr); in TEST()
286 TEST(CLUSTERS, midr) { in TEST() argument
290 ASSERT_EQ(UINT32_C(0x410FC0E0), cpuinfo_get_cluster(i)->midr); in TEST()
293 ASSERT_EQ(UINT32_C(0x410FC075), cpuinfo_get_cluster(i)->midr); in TEST()
Dnexus6p.cc190 TEST(CORES, midr) { in TEST() argument
197 ASSERT_EQ(UINT32_C(0x411FD071), cpuinfo_get_core(i)->midr); in TEST()
203 ASSERT_EQ(UINT32_C(0x410FD032), cpuinfo_get_core(i)->midr); in TEST()
305 TEST(CLUSTERS, midr) { in TEST() argument
309 ASSERT_EQ(UINT32_C(0x411FD071), cpuinfo_get_cluster(i)->midr); in TEST()
312 ASSERT_EQ(UINT32_C(0x410FD032), cpuinfo_get_cluster(i)->midr); in TEST()
Dgalaxy-s5-global.cc190 TEST(CORES, midr) { in TEST() argument
197 ASSERT_EQ(UINT32_C(0x412FC0F3), cpuinfo_get_core(i)->midr); in TEST()
203 ASSERT_EQ(UINT32_C(0x410FC073), cpuinfo_get_core(i)->midr); in TEST()
305 TEST(CLUSTERS, midr) { in TEST() argument
309 ASSERT_EQ(UINT32_C(0x412FC0F3), cpuinfo_get_cluster(i)->midr); in TEST()
312 ASSERT_EQ(UINT32_C(0x410FC073), cpuinfo_get_cluster(i)->midr); in TEST()
Dpixel-xl.cc161 TEST(CORES, midr) { in TEST() argument
166 ASSERT_EQ(UINT32_C(0x512F2051), cpuinfo_get_core(i)->midr); in TEST()
170 ASSERT_EQ(UINT32_C(0x512F2011), cpuinfo_get_core(i)->midr); in TEST()
261 TEST(CLUSTERS, midr) { in TEST() argument
265 ASSERT_EQ(UINT32_C(0x512F2051), cpuinfo_get_cluster(i)->midr); in TEST()
268 ASSERT_EQ(UINT32_C(0x512F2011), cpuinfo_get_cluster(i)->midr); in TEST()
Doppo-r15.cc190 TEST(CORES, midr) { in TEST() argument
197 ASSERT_EQ(UINT32_C(0x410FD092), cpuinfo_get_core(i)->midr); in TEST()
203 ASSERT_EQ(UINT32_C(0x410FD034), cpuinfo_get_core(i)->midr); in TEST()
292 TEST(CLUSTERS, midr) { in TEST() argument
296 ASSERT_EQ(UINT32_C(0x410FD092), cpuinfo_get_cluster(i)->midr); in TEST()
299 ASSERT_EQ(UINT32_C(0x410FD034), cpuinfo_get_cluster(i)->midr); in TEST()
Dgalaxy-s7-us.cc161 TEST(CORES, midr) { in TEST() argument
166 ASSERT_EQ(UINT32_C(0x511F2052), cpuinfo_get_core(i)->midr); in TEST()
170 ASSERT_EQ(UINT32_C(0x511F2112), cpuinfo_get_core(i)->midr); in TEST()
261 TEST(CLUSTERS, midr) { in TEST() argument
265 ASSERT_EQ(UINT32_C(0x511F2052), cpuinfo_get_cluster(i)->midr); in TEST()
268 ASSERT_EQ(UINT32_C(0x511F2112), cpuinfo_get_cluster(i)->midr); in TEST()
/external/XNNPACK/third_party/
Dcpuinfo.patch130 - switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) {
143 + switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) {
175 uint32_t midr,
214 - switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) {
230 + switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) {
342 uint32_t midr,
438 diff --git src/arm/midr.h src/arm/midr.h
440 --- src/arm/midr.h
441 +++ src/arm/midr.h
442 @@ -171,9 +171,10 @@ inline static bool midr_is_kryo_gold(uint32_t midr) {
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