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Searched refs:mmio_clrsetbits_32 (Results 1 – 25 of 49) sorted by relevance

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/external/arm-trusted-firmware/plat/brcm/board/stingray/driver/ext_sram_init/
Dext_sram_init.c24 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2dc), in brcm_stingray_pnor_pinmux_init()
29 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2e0), in brcm_stingray_pnor_pinmux_init()
34 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2e4), in brcm_stingray_pnor_pinmux_init()
39 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2e8), in brcm_stingray_pnor_pinmux_init()
44 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2ec), in brcm_stingray_pnor_pinmux_init()
49 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2f0), in brcm_stingray_pnor_pinmux_init()
54 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2f4), in brcm_stingray_pnor_pinmux_init()
59 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2f8), in brcm_stingray_pnor_pinmux_init()
64 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2fc), in brcm_stingray_pnor_pinmux_init()
69 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x300), in brcm_stingray_pnor_pinmux_init()
[all …]
/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/
Ddfs.c500 mmio_clrsetbits_32(CTL_REG(i, 22), 0xffff, in gen_rk3399_ctl_params_f0()
507 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
516 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
524 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
529 mmio_clrsetbits_32(CTL_REG(i, 23), (0x7f << 16), in gen_rk3399_ctl_params_f0()
531 mmio_clrsetbits_32(CTL_REG(i, 23), (0x1f << 24), in gen_rk3399_ctl_params_f0()
533 mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f, pdram_timing->al); in gen_rk3399_ctl_params_f0()
534 mmio_clrsetbits_32(CTL_REG(i, 26), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
543 mmio_clrsetbits_32(CTL_REG(i, 31), 0xffu << 24, in gen_rk3399_ctl_params_f0()
547 mmio_clrsetbits_32(CTL_REG(i, 34), 0xff, in gen_rk3399_ctl_params_f0()
[all …]
Dsuspend.c151 mmio_clrsetbits_32(PHY_REG(ch, 8 + (128 * byte)), 0x1 << 24, in set_cs_training_index()
172 mmio_clrsetbits_32(PHY_REG(ch, 8 + (128 * byte)), 0x1 << 16, in override_write_leveling_value()
174 mmio_clrsetbits_32(PHY_REG(ch, 63 + (128 * byte)), in override_write_leveling_value()
180 mmio_clrsetbits_32(CTL_REG(ch, 200), 0x1 << 8, 0x1 << 8); in override_write_leveling_value()
224 mmio_clrsetbits_32(PI_REG(ch, 100), 0x3 << 8, 0x2 << 8); in data_training()
227 mmio_clrsetbits_32(PI_REG(ch, 92), in data_training()
265 mmio_clrsetbits_32(PI_REG(ch, 60), 0x3 << 8, 0x2 << 8); in data_training()
267 mmio_clrsetbits_32(PI_REG(ch, 59), in data_training()
311 mmio_clrsetbits_32(PI_REG(ch, 80), 0x3 << 24, in data_training()
317 mmio_clrsetbits_32(PI_REG(ch, 74), in data_training()
[all …]
/external/arm-trusted-firmware/plat/mediatek/mt8192/drivers/dcm/
Dmtk_dcm_utils.c63 mmio_clrsetbits_32(MP_ADB_DCM_CFG0, in dcm_mp_cpusys_top_adb_dcm()
66 mmio_clrsetbits_32(MP_ADB_DCM_CFG4, in dcm_mp_cpusys_top_adb_dcm()
69 mmio_clrsetbits_32(MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_adb_dcm()
74 mmio_clrsetbits_32(MP_ADB_DCM_CFG0, in dcm_mp_cpusys_top_adb_dcm()
77 mmio_clrsetbits_32(MP_ADB_DCM_CFG4, in dcm_mp_cpusys_top_adb_dcm()
80 mmio_clrsetbits_32(MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_adb_dcm()
117 mmio_clrsetbits_32(MP_MISC_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
120 mmio_clrsetbits_32(MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
123 mmio_clrsetbits_32(MP0_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
128 mmio_clrsetbits_32(MP_MISC_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
[all …]
/external/arm-trusted-firmware/plat/brcm/board/stingray/src/
Dsdio.c70 mmio_clrsetbits_32(sdio0_cfg->pad_base + PAD_SDIO_CLK, in brcm_stingray_sdio_init()
72 mmio_clrsetbits_32(sdio0_cfg->pad_base + PAD_SDIO_DATA0, in brcm_stingray_sdio_init()
74 mmio_clrsetbits_32(sdio0_cfg->pad_base + PAD_SDIO_DATA1, in brcm_stingray_sdio_init()
76 mmio_clrsetbits_32(sdio0_cfg->pad_base + PAD_SDIO_DATA2, in brcm_stingray_sdio_init()
78 mmio_clrsetbits_32(sdio0_cfg->pad_base + PAD_SDIO_DATA3, in brcm_stingray_sdio_init()
80 mmio_clrsetbits_32(sdio0_cfg->pad_base + PAD_SDIO_DATA4, in brcm_stingray_sdio_init()
82 mmio_clrsetbits_32(sdio0_cfg->pad_base + PAD_SDIO_DATA5, in brcm_stingray_sdio_init()
84 mmio_clrsetbits_32(sdio0_cfg->pad_base + PAD_SDIO_DATA6, in brcm_stingray_sdio_init()
86 mmio_clrsetbits_32(sdio0_cfg->pad_base + PAD_SDIO_DATA7, in brcm_stingray_sdio_init()
88 mmio_clrsetbits_32(sdio0_cfg->pad_base + PAD_SDIO_CMD, in brcm_stingray_sdio_init()
[all …]
Dbl31_setup.c325 mmio_clrsetbits_32(ICFG_AMAC_RGMII_PHY_CONFIG, AMAC_RPHY_SPEED_MASK, in brcm_stingray_amac_init()
337 mmio_clrsetbits_32(AMAC_IDM0_IO_CONTROL_DIRECT, AMAC_IDM0_ARCACHE_MASK, in brcm_stingray_amac_init()
339 mmio_clrsetbits_32(AMAC_IDM0_IO_CONTROL_DIRECT, AMAC_IDM0_AWCACHE_MASK, in brcm_stingray_amac_init()
498 mmio_clrsetbits_32(scr_base + 0x0, clr_mask, set_mask); in brcm_stingray_scr_init()
503 mmio_clrsetbits_32(scr_base + 0x4, clr_mask, set_mask); in brcm_stingray_scr_init()
508 mmio_clrsetbits_32(scr_base + 0x8, clr_mask, set_mask); in brcm_stingray_scr_init()
513 mmio_clrsetbits_32(scr_base + 0xc, clr_mask, set_mask); in brcm_stingray_scr_init()
518 mmio_clrsetbits_32(scr_base + 0x10, clr_mask, set_mask); in brcm_stingray_scr_init()
589 mmio_clrsetbits_32(I2S_IDM_IO_CONTROL, I2S_IDM0_ARCACHE_MASK, in brcm_stingray_audio_init()
592 mmio_clrsetbits_32(I2S_IDM_IO_CONTROL, I2S_IDM0_AWCACHE_MASK, in brcm_stingray_audio_init()
Dihost_pm.c158 mmio_clrsetbits_32(ihost_base + A72_CRM_DOMAIN_4_CONTROL, in ihost_power_on_cluster()
168 mmio_clrsetbits_32(ihost_base + A72_CRM_DOMAIN_0_CONTROL, in ihost_power_on_cluster()
173 mmio_clrsetbits_32(ihost_base + A72_CRM_DOMAIN_1_CONTROL, in ihost_power_on_cluster()
Dncsi.c49 mmio_clrsetbits_32((NITRO_NCSI_IOPAD_CONTROL_BASE + (i * 4)), in brcm_stingray_ncsi_init()
/external/arm-trusted-firmware/plat/mediatek/mt8183/
Dbl31_plat_setup.c49 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en, in platform_setup_cpu()
51 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en, in platform_setup_cpu()
54 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->cci_adb400_dcm_config, in platform_setup_cpu()
60 mmio_clrsetbits_32( in platform_setup_cpu()
68 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_config, in platform_setup_cpu()
74 mmio_clrsetbits_32( in platform_setup_cpu()
Dplat_mt_gic.c145 mmio_clrsetbits_32(GIC_SYNC_DCM, GIC_SYNC_DCM_MASK, GIC_SYNC_DCM_ON); in mt_gic_sync_dcm_enable()
150 mmio_clrsetbits_32(GIC_SYNC_DCM, GIC_SYNC_DCM_MASK, GIC_SYNC_DCM_OFF); in mt_gic_sync_dcm_disable()
/external/arm-trusted-firmware/plat/mediatek/mt8183/drivers/devapc/
Ddevapc.c46 mmio_clrsetbits_32(base, clr_bit, set_bit); in set_master_domain()
60 mmio_clrsetbits_32(base, clr_bit, set_bit); in set_master_domain_remap_infra()
66 mmio_clrsetbits_32(base, clr_bit, set_bit); in set_master_domain_remap_infra()
71 mmio_clrsetbits_32(base, clr_bit, set_bit); in set_master_domain_remap_infra()
75 mmio_clrsetbits_32(base, 0x1, set_bit); in set_master_domain_remap_infra()
90 mmio_clrsetbits_32(base, clr_bit, set_bit); in set_master_domain_remap_mm()
116 mmio_clrsetbits_32(base, clr_bit, set_bit); in set_module_apc()
/external/arm-trusted-firmware/plat/intel/soc/common/soc/
Dsocfpga_emac.c21 mmio_clrsetbits_32(SOCFPGA_SYSMGR(EMAC_0), in socfpga_emac_init()
23 mmio_clrsetbits_32(SOCFPGA_SYSMGR(EMAC_1), in socfpga_emac_init()
25 mmio_clrsetbits_32(SOCFPGA_SYSMGR(EMAC_2), in socfpga_emac_init()
/external/arm-trusted-firmware/plat/imx/imx8m/
Dgpc_common.c144 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, A53_CLK_ON_LPM, in imx_set_cluster_powerdown()
163 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, 0xf, A53_CLK_ON_LPM); in imx_set_cluster_powerdown()
167 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_AD, (L2PGE | EN_PLAT_PDN), in imx_set_cluster_powerdown()
190 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, A53_CORE_WUP_SRC(last_core), in imx_set_sys_wakeup()
193 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, IRQ_SRC_A53_WUP, in imx_set_sys_wakeup()
/external/arm-trusted-firmware/drivers/marvell/mochi/
Dapn806_setup.c83 mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, 0x0U, /* no clear */ in apn_sec_masters_access_en()
89 mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, in apn_sec_masters_access_en()
96 mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, in apn_sec_masters_access_en()
101 mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, in apn_sec_masters_access_en()
Dap807_setup.c87 mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, 0x0U, /* no clear */ in ap_sec_masters_access_en()
93 mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, in ap_sec_masters_access_en()
100 mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, in ap_sec_masters_access_en()
105 mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, in ap_sec_masters_access_en()
Dcp110_setup.c324 mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG, in cp110_rtc_init()
328 mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG, in cp110_rtc_init()
333 mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL1_REG, in cp110_rtc_init()
/external/arm-trusted-firmware/plat/allwinner/common/
Dsunxi_common.c100 mmio_clrsetbits_32(port_base + (pin / 8) * 4, in sunxi_set_gpio_out()
137 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x00, 0xffU, pin_func); in sunxi_init_platform_r_twi()
140 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x14, 0x0fU, 0xaU); in sunxi_init_platform_r_twi()
143 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x1c, 0x0fU, 0x5U); in sunxi_init_platform_r_twi()
/external/arm-trusted-firmware/plat/intel/soc/stratix10/soc/
Ds10_memory_controller.c226 mmio_clrsetbits_32( in configure_ddr_sched_ctrl_regs()
376 mmio_clrsetbits_32(S10_MPFE_HMC_ADP_DDRIOCTRL, in configure_hmc_adaptor_regs()
385 mmio_clrsetbits_32(S10_MPFE_HMC_ADP_ECCCTRL1, in configure_hmc_adaptor_regs()
392 mmio_clrsetbits_32(S10_MPFE_HMC_ADP_ECCCTRL2, in configure_hmc_adaptor_regs()
399 mmio_clrsetbits_32(S10_MPFE_HMC_ADP_ECCCTRL1, in configure_hmc_adaptor_regs()
/external/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/
Dspm_hotplug.c251 mmio_clrsetbits_32(SPM_PCM_RESERVE, in spm_hotplug_on()
271 mmio_clrsetbits_32(SPM_PCM_RESERVE, PCM_HOTPLUG_VALID_MASK, in spm_hotplug_off()
Dspm.c171 mmio_clrsetbits_32(SPM_CLK_CON, CC_SRCLKENA_MASK_0, in spm_set_power_control()
294 mmio_clrsetbits_32(SPM_CLK_CON, CC_LOCK_INFRA_DCM, in spm_kick_pcm_to_run()
304 mmio_clrsetbits_32(SPM_PCM_CON1, CON1_PCM_WDT_EN, CON1_CFG_KEY); in spm_clean_after_wakeup()
308 mmio_clrsetbits_32(SPM_PCM_CON1, CON1_PCM_TIMER_EN, CON1_CFG_KEY); in spm_clean_after_wakeup()
/external/arm-trusted-firmware/plat/intel/soc/agilex/soc/
Dagilex_memory_controller.c197 mmio_clrsetbits_32( in configure_ddr_sched_ctrl_regs()
373 mmio_clrsetbits_32(AGX_MPFE_HMC_ADP_ECCCTRL1, in configure_hmc_adaptor_regs()
380 mmio_clrsetbits_32(AGX_MPFE_HMC_ADP_ECCCTRL2, in configure_hmc_adaptor_regs()
387 mmio_clrsetbits_32(AGX_MPFE_HMC_ADP_ECCCTRL1, in configure_hmc_adaptor_regs()
/external/arm-trusted-firmware/plat/mediatek/mt8183/drivers/spm/
Dspm.c225 mmio_clrsetbits_32(PCM_CON1, PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY); in spm_disable_pcm_timer()
256 mmio_clrsetbits_32(PCM_CON1, PCM_WDT_WAKE_MODE_LSB, in spm_set_pcm_wdt()
265 mmio_clrsetbits_32(PCM_CON1, PCM_WDT_EN_LSB, in spm_set_pcm_wdt()
349 mmio_clrsetbits_32(SPM_DVS_LEVEL, in spm_boot_init()
/external/arm-trusted-firmware/plat/imx/imx8m/imx8mq/
Dgpc.c66 mmio_clrsetbits_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, 0xFFFFFFFF, in imx_pup_pdn_slot_config()
72 mmio_clrsetbits_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, 0xFFFFFFFF, in imx_pup_pdn_slot_config()
/external/arm-trusted-firmware/plat/brcm/board/stingray/include/
Dsr_utils.h33 mmio_clrsetbits_32(CDRU_CHIP_STRAP_DATA, in brcm_stingray_set_straps()
/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/include/
Drk3399_mcu.h22 #define mmio_clrsetbits_32(addr, clear, set) \ macro

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