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Searched refs:nir_component_mask_t (Results 1 – 16 of 16) sorted by relevance

/external/mesa3d/src/compiler/nir/
Dnir_opt_dead_write_vars.c51 nir_component_mask_t mask;
76 nir_deref_instr *dst, nir_component_mask_t mask) in update_unused_writes()
193 nir_component_mask_t mask = nir_intrinsic_write_mask(intrin); in remove_dead_write_vars_local()
216 nir_component_mask_t mask = (1 << glsl_get_vector_elements(dst->type)) - 1; in remove_dead_write_vars_local()
Dnir_lower_ubo_vec4.c148 nir_component_mask_t low_channels = in nir_lower_ubo_vec4_lower()
150 nir_component_mask_t high_channels = in nir_lower_ubo_vec4_lower()
Dnir_split_vars.c970 nir_component_mask_t all_comps;
972 nir_component_mask_t comps_read;
973 nir_component_mask_t comps_written;
975 nir_component_mask_t comps_kept;
1071 nir_component_mask_t comps_read, in mark_deref_used()
1072 nir_component_mask_t comps_written, in mark_deref_used()
1182 static nir_component_mask_t
1185 nir_component_mask_t comps = nir_intrinsic_write_mask(store); in get_non_self_referential_store_comps()
1333 nir_component_mask_t comps_kept = in shrink_vec_var_list()
1591 nir_component_mask_t write_mask = in shrink_vec_var_access_impl()
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Dnir_opt_copy_prop_vars.c192 nir_component_mask_t mask = in gather_vars_written()
193 (nir_component_mask_t) BITFIELD_MASK(glsl_get_vector_elements(payload->type)); in gather_vars_written()
298 nir_component_mask_t merged = (uintptr_t) new_entry->data | in gather_vars_written()
543 nir_component_mask_t available = 0; in load_from_ssa_entry_value()
1117 nir_component_mask_t full_mask = in copy_prop_vars_block()
1118 (nir_component_mask_t) BITFIELD_MASK(glsl_get_vector_elements(payload->type)); in copy_prop_vars_block()
Dnir_lower_fragcolor.c68 nir_component_mask_t writemask = nir_intrinsic_write_mask(instr); in lower_fragcolor_instr()
Dnir_opt_combine_stores.c55 nir_component_mask_t write_mask;
275 nir_component_mask_t prev_mask = nir_intrinsic_write_mask(prev_store); in update_combined_store()
Dnir_lower_io_to_vector.c455 nir_component_mask_t vec4_comp_mask = in nir_lower_io_to_vector_impl()
525 nir_component_mask_t old_wrmask = nir_intrinsic_write_mask(intrin); in nir_lower_io_to_vector_impl()
Dnir.c44 nir_component_mask_can_reinterpret(nir_component_mask_t mask, in nir_component_mask_can_reinterpret()
79 nir_component_mask_t
80 nir_component_mask_reinterpret(nir_component_mask_t mask, in nir_component_mask_reinterpret()
89 nir_component_mask_t new_mask = 0; in nir_component_mask_reinterpret()
1666 nir_component_mask_t
1669 nir_component_mask_t read_mask = 0; in nir_ssa_def_components_read()
Dnir_deref.c1130 nir_component_mask_t mask, in is_vector_bitcast_deref()
1192 nir_component_mask_t read_mask = in opt_load_vec_deref()
1233 nir_component_mask_t write_mask = nir_intrinsic_write_mask(store); in opt_store_vec_deref()
Dnir.h68 typedef uint16_t nir_component_mask_t; typedef
79 bool nir_component_mask_can_reinterpret(nir_component_mask_t mask,
82 nir_component_mask_t
83 nir_component_mask_reinterpret(nir_component_mask_t mask,
1381 static inline nir_component_mask_t
1384 nir_component_mask_t read_mask = 0; in nir_alu_instr_src_read_mask()
4015 nir_component_mask_t nir_ssa_def_components_read(const nir_ssa_def *def);
Dnir_lower_io.c389 nir_component_mask_t write_mask, nir_alu_type src_type) in emit_store()
460 nir_component_mask_t write_mask = nir_intrinsic_write_mask(intrin); in lower_store()
472 nir_component_mask_t write_mask32 = 0; in lower_store()
1420 nir_ssa_def *value, nir_component_mask_t write_mask) in build_explicit_io_store()
1787 nir_component_mask_t write_mask = nir_intrinsic_write_mask(intrin); in nir_lower_explicit_io_instr()
1822 const nir_component_mask_t write_mask = 0; in nir_lower_explicit_io_instr()
Dnir_builder.h633 nir_channels(nir_builder *b, nir_ssa_def *def, nir_component_mask_t mask) in nir_channels()
1318 nir_ssa_def *def, nir_component_mask_t write_mask) in nir_store_reg()
1473 nir_ssa_def *value, nir_component_mask_t write_mask) in nir_store_global()
Dnir_print.c193 nir_component_mask_t used_channels = 0; in print_alu_src()
/external/mesa3d/src/intel/compiler/
Dbrw_nir_lower_mem_access_bit_sizes.c171 nir_component_mask_t writemask = nir_intrinsic_write_mask(intrin); in lower_mem_store_bit_size()
/external/mesa3d/src/gallium/drivers/r600/sfn/
Dsfn_instruction_tex.cpp261 (nir_component_mask_t)cmp_mask)); in lower_txl_txf_array_or_cube()
/external/mesa3d/src/compiler/nir/tests/
Dvars_tests.cpp213 nir_ssa_def *value, nir_component_mask_t writemask) in nir_store_var_volatile()
1654 nir_component_mask_t mask = (1 << i) | (1 << (i + 1)); in TEST_F()