| /external/mesa3d/src/gallium/drivers/iris/ |
| D | iris_genx_macros.h | 104 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \ argument
106 uint32_t *dw = __gen_get_batch_dwords(batch, num_dwords); \
107 for (uint32_t i = 0; i < num_dwords; i++) \
109 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
|
| D | iris_state.c | 5451 const uint32_t num_dwords = 2 + 2 * n; in emit_push_constant_packet_all() local
5457 all.DWordLength = num_dwords - 2; in emit_push_constant_packet_all()
5471 iris_batch_emit(batch, const_all, sizeof(uint32_t) * num_dwords); in emit_push_constant_packet_all()
|
| /external/mesa3d/src/gallium/drivers/virgl/ |
| D | virgl_transfer_queue.c | 179 queue->num_dwords -= (VIRGL_TRANSFER3D_SIZE + 1); in replace_unmapped_transfer()
246 if (queue->num_dwords + dwords >= VIRGL_MAX_TBUF_DWORDS) { in add_internal()
256 queue->num_dwords = 0; in add_internal()
261 queue->num_dwords += dwords; in add_internal()
271 queue->num_dwords = 0; in virgl_transfer_queue_init()
298 queue->num_dwords = 0; in virgl_transfer_queue_fini()
343 queue->num_dwords = 0; in virgl_transfer_queue_clear()
|
| D | virgl_transfer_queue.h | 40 uint32_t num_dwords; member
|
| D | virgl_context.c | 918 ctx->queue.num_dwords == 0 && in virgl_flush_eq()
|
| /external/mesa3d/src/intel/common/tests/ |
| D | gen_mi_builder_test.cpp | 47 void * __gen_get_batch_dwords(gen_mi_builder_test *test, unsigned num_dwords);
88 void *emit_dwords(int num_dwords);
256 gen_mi_builder_test::emit_dwords(int num_dwords) in emit_dwords() argument
259 batch_offset += num_dwords * 4; in emit_dwords()
324 __gen_get_batch_dwords(gen_mi_builder_test *test, unsigned num_dwords) in __gen_get_batch_dwords() argument
326 return test->emit_dwords(num_dwords); in __gen_get_batch_dwords()
|
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_test_dma_perf.c | 221 unsigned num_dwords = size / 4; in si_test_dma_perf() local
222 unsigned num_instructions = DIV_ROUND_UP(num_dwords, dwords_per_instruction); in si_test_dma_perf()
228 info.grid[0] = DIV_ROUND_UP(num_dwords, dwords_per_wave); in si_test_dma_perf()
|
| D | si_compute_blit.c | 219 unsigned num_dwords = size / 4; in si_compute_do_clear_or_copy() local
220 unsigned num_instructions = DIV_ROUND_UP(num_dwords, dwords_per_instruction); in si_compute_do_clear_or_copy()
226 info.grid[0] = DIV_ROUND_UP(num_dwords, dwords_per_wave); in si_compute_do_clear_or_copy()
|
| D | si_descriptors.c | 1713 unsigned num_dwords) in si_upload_bindless_descriptor() argument
1723 si_cp_write_data(sctx, desc->buffer, va - desc->buffer->gpu_address, num_dwords * 4, V_370_TC_L2, in si_upload_bindless_descriptor()
|
| /external/mesa3d/src/amd/common/ |
| D | sid.h | 199 #define EOP_DATA_GDS(dw_offset, num_dwords) ((dw_offset) | ((unsigned)(num_dwords) << 16)) argument
|
| /external/mesa3d/src/amd/vulkan/ |
| D | radv_sqtt.c | 347 const void *data, uint32_t num_dwords) in radv_emit_thread_trace_userdata() argument
351 while (num_dwords > 0) { in radv_emit_thread_trace_userdata()
352 uint32_t count = MIN2(num_dwords, 2); in radv_emit_thread_trace_userdata()
363 num_dwords -= count; in radv_emit_thread_trace_userdata()
|
| D | radv_private.h | 2523 const void *data, uint32_t num_dwords);
|
| /external/mesa3d/src/intel/common/ |
| D | gen_mi_builder.h | 631 unsigned num_dwords) in _gen_mi_builder_push_math() argument
633 assert(num_dwords < GEN_MI_BUILDER_MAX_MATH_DWORDS); in _gen_mi_builder_push_math()
634 if (b->num_math_dwords + num_dwords > GEN_MI_BUILDER_MAX_MATH_DWORDS) in _gen_mi_builder_push_math()
638 dwords, num_dwords * sizeof(*dwords)); in _gen_mi_builder_push_math()
639 b->num_math_dwords += num_dwords; in _gen_mi_builder_push_math()
|
| /external/mesa3d/src/intel/blorp/ |
| D | blorp_genX_exec.h | 398 const unsigned num_dwords = 1 + num_vbs * GENX(VERTEX_BUFFER_STATE_length); in blorp_emit_vertex_buffers() local
399 uint32_t *dw = blorp_emitn(batch, GENX(3DSTATE_VERTEX_BUFFERS), num_dwords); in blorp_emit_vertex_buffers()
547 const unsigned num_dwords = in blorp_emit_vertex_elements() local
549 uint32_t *dw = blorp_emitn(batch, GENX(3DSTATE_VERTEX_ELEMENTS), num_dwords); in blorp_emit_vertex_elements()
1878 const unsigned num_dwords = GENX(MI_ATOMIC_length) + inlinedata_dw; in blorp_update_clear_color() local
1881 uint32_t *dw = blorp_emitn(batch, GENX(MI_ATOMIC), num_dwords, in blorp_update_clear_color()
1893 dw = blorp_emitn(batch, GENX(MI_ATOMIC), num_dwords, in blorp_update_clear_color()
|
| /external/mesa3d/src/intel/compiler/ |
| D | brw_eu.h | 787 unsigned num_dwords, in brw_dp_oword_block_rw_desc() argument
799 SET_BITS(BRW_DATAPORT_OWORD_BLOCK_DWORDS(num_dwords), 2, 0); in brw_dp_oword_block_rw_desc()
832 unsigned num_dwords, in brw_dp_a64_oword_block_rw_desc() argument
844 SET_BITS(BRW_DATAPORT_OWORD_BLOCK_DWORDS(num_dwords), 2, 0); in brw_dp_a64_oword_block_rw_desc()
|
| /external/mesa3d/src/intel/vulkan/ |
| D | genX_pipeline.c | 113 const uint32_t num_dwords = 1 + total_elems * 2; in emit_vertex_input() local
114 p = anv_batch_emitn(&pipeline->base.batch, num_dwords, in emit_vertex_input()
1139 const uint32_t num_dwords = GENX(BLEND_STATE_length) + local
1142 anv_state_pool_alloc(&device->dynamic_state_pool, num_dwords * 4, 64);
|
| D | anv_batch_chain.c | 262 anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords) in anv_batch_emit_dwords() argument
264 if (batch->next + num_dwords * 4 > batch->end) { in anv_batch_emit_dwords()
274 batch->next += num_dwords * 4; in anv_batch_emit_dwords()
|
| D | genX_cmd_buffer.c | 1001 const unsigned num_dwords = GEN_GEN >= 10 ? in init_fast_clear_color() local
1004 for (unsigned i = 0; i < num_dwords; i++) { in init_fast_clear_color()
3261 const uint32_t num_dwords = 2 + 2 * buffer_count; in cmd_buffer_emit_push_constant_all() local
3263 dw = anv_batch_emitn(&cmd_buffer->batch, num_dwords, in cmd_buffer_emit_push_constant_all()
3467 const uint32_t num_dwords = 1 + num_buffers * 4; in genX() local
3469 p = anv_batch_emitn(&cmd_buffer->batch, num_dwords, in genX()
|
| D | anv_private.h | 1700 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
|