Searched refs:reg_mode (Results 1 – 7 of 7) sorted by relevance
| /external/mesa3d/src/panfrost/midgard/ |
| D | midgard_print_constant.c | 34 midgard_reg_mode reg_mode, bool half, in mir_print_constant_component() argument
63 reg_mode--; in mir_print_constant_component()
65 switch (reg_mode) { in mir_print_constant_component()
|
| D | midgard_emit.c | 198 nir_alu_type T, midgard_reg_mode reg_mode, in mir_pack_swizzle() argument
204 if (reg_mode == midgard_reg_mode_64) { in mir_pack_swizzle()
263 if (reg_mode == midgard_reg_mode_16 && sz == 16) { in mir_pack_swizzle()
266 } else if (reg_mode == midgard_reg_mode_16 && sz == 8) { in mir_pack_swizzle()
269 } else if (reg_mode == midgard_reg_mode_32) { in mir_pack_swizzle()
577 .reg_mode = reg_mode_for_bitsize(max_bitsize_for_alu(ins)) in vector_alu_from_instr()
|
| D | midgard_print.c | 121 midgard_reg_mode reg_mode = reg_mode_for_bitsize(max_bitsize_for_alu(ins)); in mir_print_embedded_constant() local
142 swizzle[comp], reg_mode, in mir_print_embedded_constant()
|
| D | helpers.h | 349 unsigned c, midgard_reg_mode reg_mode, bool half,
|
| D | midgard.h | 266 midgard_reg_mode reg_mode : 2; member
|
| D | disassemble.c | 369 unsigned bits = bits_for_mode_halved(alu->reg_mode, src->half); in print_vector_constants()
417 mir_print_constant_component(fp, consts, c, alu->reg_mode, in print_vector_constants()
635 midgard_reg_mode mode = alu_field->reg_mode; in print_vector_field()
|
| /external/mesa3d/docs/relnotes/ |
| D | 20.2.0.rst | 2452 - pan/mdg: eliminate references to ins->alu.reg_mode
|