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/external/llvm-project/llvm/test/Analysis/CostModel/SystemZ/
Dfp-arith.ll19 %res7 = fadd <8 x float> undef, undef
33 ; CHECK-Z13: Cost Model: Found an estimated cost of 16 for instruction: %res7 = fadd <8 x float> …
34 ; CHECK-Z14: Cost Model: Found an estimated cost of 2 for instruction: %res7 = fadd <8 x float> u…
51 %res7 = fsub <8 x float> undef, undef
65 ; CHECK-Z13: Cost Model: Found an estimated cost of 16 for instruction: %res7 = fsub <8 x float> …
66 ; CHECK-Z14: Cost Model: Found an estimated cost of 2 for instruction: %res7 = fsub <8 x float> u…
83 %res7 = fmul <8 x float> undef, undef
97 ; CHECK-Z13: Cost Model: Found an estimated cost of 16 for instruction: %res7 = fmul <8 x float> …
98 ; CHECK-Z14: Cost Model: Found an estimated cost of 2 for instruction: %res7 = fmul <8 x float> u…
115 %res7 = fdiv <8 x float> undef, undef
[all …]
Dlogical.ll11 %res7 = and <2 x i64> undef, undef
32 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res7 = and <2 x i64> undef, u…
57 %res7 = ashr <2 x i64> undef, undef
78 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res7 = ashr <2 x i64> undef, …
103 %res7 = lshr <2 x i64> undef, undef
124 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res7 = lshr <2 x i64> undef, …
149 %res7 = or <2 x i64> undef, undef
170 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res7 = or <2 x i64> undef, un…
195 %res7 = shl <2 x i64> undef, undef
216 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res7 = shl <2 x i64> undef, u…
[all …]
Dint-arith.ll14 %res7 = add <2 x i64> undef, undef
35 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res7 = add <2 x i64> undef, u…
60 %res7 = sub <2 x i64> undef, undef
81 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res7 = sub <2 x i64> undef, u…
106 %res7 = mul <2 x i64> undef, undef
127 ; CHECK: Cost Model: Found an estimated cost of 3 for instruction: %res7 = mul <2 x i64> undef, u…
/external/libvpx/libvpx/vpx_dsp/mips/
Didct16x16_msa.c267 v8i16 vec, res0, res1, res2, res3, res4, res5, res6, res7; in vpx_idct16x16_1_add_msa() local
281 UNPCK_UB_SH(dst3, res3, res7); in vpx_idct16x16_1_add_msa()
283 ADD4(res4, vec, res5, vec, res6, vec, res7, vec, res4, res5, res6, res7); in vpx_idct16x16_1_add_msa()
285 CLIP_SH4_0_255(res4, res5, res6, res7); in vpx_idct16x16_1_add_msa()
286 PCKEV_B4_UB(res4, res0, res5, res1, res6, res2, res7, res3, tmp0, tmp1, in vpx_idct16x16_1_add_msa()
331 v8i16 res0, res1, res2, res3, res4, res5, res6, res7; in vpx_iadst16_1d_columns_addblk_msa() local
445 ILVR_B2_SH(zero, dst6, zero, dst7, res6, res7); in vpx_iadst16_1d_columns_addblk_msa()
446 ADD2(res6, out6, res7, out7, res6, res7); in vpx_iadst16_1d_columns_addblk_msa()
447 CLIP_SH2_0_255(res6, res7); in vpx_iadst16_1d_columns_addblk_msa()
448 PCKEV_B2_SH(res6, res6, res7, res7, res6, res7); in vpx_iadst16_1d_columns_addblk_msa()
[all …]
Dvpx_convolve8_avg_horiz_msa.c497 v8u16 res0, res1, res2, res3, res4, res5, res6, res7, filt; in common_hz_2t_and_aver_dst_16w_msa() local
516 res6, res7); in common_hz_2t_and_aver_dst_16w_msa()
518 SRARI_H4_UH(res4, res5, res6, res7, FILTER_BITS); in common_hz_2t_and_aver_dst_16w_msa()
526 PCKEV_AVG_ST_UB(res7, res6, dst3, dst); in common_hz_2t_and_aver_dst_16w_msa()
541 res6, res7); in common_hz_2t_and_aver_dst_16w_msa()
543 SRARI_H4_UH(res4, res5, res6, res7, FILTER_BITS); in common_hz_2t_and_aver_dst_16w_msa()
551 PCKEV_AVG_ST_UB(res7, res6, dst3, dst); in common_hz_2t_and_aver_dst_16w_msa()
564 v8u16 res0, res1, res2, res3, res4, res5, res6, res7, filt; in common_hz_2t_and_aver_dst_32w_msa() local
591 res6, res7); in common_hz_2t_and_aver_dst_32w_msa()
593 SRARI_H4_UH(res4, res5, res6, res7, FILTER_BITS); in common_hz_2t_and_aver_dst_32w_msa()
[all …]
/external/libaom/libaom/av1/common/arm/
Djnt_convolve_neon.c443 int16x8_t res1, res2, res3, res4, res5, res6, res7; in dist_wtd_convolve_2d_horiz_neon() local
500 res7 = convolve8_8x8_s16(s7, s8, s9, s10, s11, s12, s13, s14, in dist_wtd_convolve_2d_horiz_neon()
504 &res7); in dist_wtd_convolve_2d_horiz_neon()
507 res6, res7); in dist_wtd_convolve_2d_horiz_neon()
594 uint16x4_t res5, res6, res7, d1, d2, d3; in dist_wtd_convolve_2d_vert_neon() local
647 load_u16_4x4(d, dst_stride, &res4, &res5, &res6, &res7); in dist_wtd_convolve_2d_vert_neon()
650 compute_avg_4x4(res4, res5, res6, res7, d0, d1, d2, d3, fwd_offset, in dist_wtd_convolve_2d_vert_neon()
762 uint16x4_t tmp4, tmp5, tmp6, tmp7, res4, res5, res6, res7; in av1_dist_wtd_convolve_2d_copy_neon() local
845 res7 = vadd_u16(vshl_u16(vget_low_u16(vmovl_u8(res3_8)), dup_bits16x4), in av1_dist_wtd_convolve_2d_copy_neon()
850 compute_avg_4x4(tmp4, tmp5, tmp6, tmp7, res4, res5, res6, res7, in av1_dist_wtd_convolve_2d_copy_neon()
[all …]
Dwiener_convolve_neon.c83 uint16x8_t res5, res6, res7, res8, res9, res10, res11; in av1_wiener_convolve_add_src_neon() local
143 res7 = wiener_convolve8_horiz_8x8(res0, res1, res2, res3, filter_x_tmp, in av1_wiener_convolve_add_src_neon()
174 transpose_u16_8x8(&res4, &res5, &res6, &res7, &res8, &res9, &res10, in av1_wiener_convolve_add_src_neon()
176 store_u16_8x8(d_tmp, MAX_SB_SIZE, res4, res5, res6, res7, res8, res9, in av1_wiener_convolve_add_src_neon()
248 uint16x4_t res0, res1, res2, res3, res4, res5, res6, res7; in av1_wiener_convolve_add_src_neon() local
319 res7 = in av1_wiener_convolve_add_src_neon()
324 &res7, &d0, &d1, &d2, &d3); in av1_wiener_convolve_add_src_neon()
/external/swiftshader/third_party/subzero/crosstest/
Dtest_vector_ops_ll.ll96 %res7 = zext <8 x i1> %res7_i1 to <8 x i16>
97 ret <8 x i16> %res7
153 %res7 = zext <16 x i1> %res7_i1 to <16 x i8>
154 ret <16 x i8> %res7
257 %res7 = insertelement <8 x i16> %vec, i16 %elt, i32 7
258 ret <8 x i16> %res7
312 %res7 = insertelement <16 x i8> %vec, i8 %elt, i32 7
313 ret <16 x i8> %res7
441 %res7 = zext i1 %res7_i1 to i64
442 ret i64 %res7
[all …]
/external/libyuv/files/source/
Drotate_msa.cc86 v16u8 res0, res1, res2, res3, res4, res5, res6, res7, res8, res9; in TransposeWx16_MSA() local
111 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7); in TransposeWx16_MSA()
149 ILVRL_D(res6, res8, res7, res9, dst0, dst1, dst2, dst3); in TransposeWx16_MSA()
167 v16u8 res0, res1, res2, res3, res4, res5, res6, res7, res8, res9; in TransposeUVWx16_MSA() local
192 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7); in TransposeUVWx16_MSA()
236 ILVRL_D(res6, res8, res7, res9, dst0, dst1, dst2, dst3); in TransposeUVWx16_MSA()
/external/libvpx/libvpx/third_party/libyuv/source/
Drotate_msa.cc86 v16u8 res0, res1, res2, res3, res4, res5, res6, res7, res8, res9; in TransposeWx16_MSA() local
111 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7); in TransposeWx16_MSA()
149 ILVRL_D(res6, res8, res7, res9, dst0, dst1, dst2, dst3); in TransposeWx16_MSA()
167 v16u8 res0, res1, res2, res3, res4, res5, res6, res7, res8, res9; in TransposeUVWx16_MSA() local
192 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7); in TransposeUVWx16_MSA()
236 ILVRL_D(res6, res8, res7, res9, dst0, dst1, dst2, dst3); in TransposeUVWx16_MSA()
/external/llvm-project/llvm/test/Bitcode/
DmiscInstructions.3.2.ll93 ; CHECK-NEXT: %res7 = icmp sgt i32 %x1, %x2
94 %res7 = icmp sgt i32 %x1, %x2
135 ; CHECK-NEXT: %res7 = fcmp ogt float %x1, %x2
136 %res7 = fcmp ogt float %x1, %x2
DmemInstructions.3.2.ll48 ; CHECK-NEXT: %res7 = load i8, i8* %ptr1, align 1, !nontemporal !0
49 %res7 = load i8, i8* %ptr1, align 1, !nontemporal !0
104 ; CHECK-NEXT: %res7 = load atomic volatile i8, i8* %ptr1 acquire, align 1
105 %res7 = load atomic volatile i8, i8* %ptr1 acquire, align 1
253 ; CHECK-NEXT: %res7 = extractvalue { i32, i1 } [[TMP]], 0
254 %res7 = cmpxchg i32* %ptr, i32 %cmp, i32 %new syncscope("singlethread") acquire acquire
/external/llvm/test/Bitcode/
DmiscInstructions.3.2.ll93 ; CHECK-NEXT: %res7 = icmp sgt i32 %x1, %x2
94 %res7 = icmp sgt i32 %x1, %x2
135 ; CHECK-NEXT: %res7 = fcmp ogt float %x1, %x2
136 %res7 = fcmp ogt float %x1, %x2
DmemInstructions.3.2.ll48 ; CHECK-NEXT: %res7 = load i8, i8* %ptr1, align 1, !nontemporal !0
49 %res7 = load i8, i8* %ptr1, align 1, !nontemporal !0
104 ; CHECK-NEXT: %res7 = load atomic volatile i8, i8* %ptr1 acquire, align 1
105 %res7 = load atomic volatile i8, i8* %ptr1 acquire, align 1
253 ; CHECK-NEXT: %res7 = extractvalue { i32, i1 } [[TMP]], 0
254 %res7 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread acquire acquire
/external/llvm-project/llvm/test/CodeGen/X86/
Dmerge-consecutive-loads-512.ll102 %res7 = insertelement <8 x double> %res1, double %val7, i32 7
103 ret <8 x double> %res7
126 %res7 = insertelement <8 x double> %res6, double 0.0, i32 7
127 ret <8 x double> %res7
155 %res7 = insertelement <8 x double> %res5, double %val7, i32 7
156 ret <8 x double> %res7
205 %res7 = insertelement <8 x i64> %res6, i64 0, i32 7
206 ret <8 x i64> %res7
234 %res7 = insertelement <8 x i64> %res5, i64 %val7, i32 7
235 ret <8 x i64> %res7
[all …]
/external/llvm/test/CodeGen/X86/
Dmerge-consecutive-loads-512.ll102 %res7 = insertelement <8 x double> %res1, double %val7, i32 7
103 ret <8 x double> %res7
134 %res7 = insertelement <8 x double> %res6, double 0.0, i32 7
135 ret <8 x double> %res7
167 %res7 = insertelement <8 x double> %res5, double %val7, i32 7
168 ret <8 x double> %res7
221 %res7 = insertelement <8 x i64> %res6, i64 0, i32 7
222 ret <8 x i64> %res7
254 %res7 = insertelement <8 x i64> %res5, i64 %val7, i32 7
255 ret <8 x i64> %res7
[all …]
Dmerge-consecutive-loads-128.ll422 %res7 = insertelement <8 x i16> %res5, i16 %val7, i32 7
423 ret <8 x i16> %res7
479 %res7 = insertelement <8 x i16> %res6, i16 0, i32 7
480 ret <8 x i16> %res7
533 %res7 = insertelement <16 x i8> %res6, i8 %val7, i32 7
534 %res8 = insertelement <16 x i8> %res7, i8 %val8, i32 8
570 %res7 = insertelement <16 x i8> %res6, i8 0, i32 7
571 %resD = insertelement <16 x i8> %res7, i8 0, i32 13
610 %res7 = insertelement <16 x i8> %res6, i8 %val7, i32 7
611 %resD = insertelement <16 x i8> %res7, i8 0, i32 13
/external/libaom/libaom/aom_dsp/x86/
Dfwd_txfm_impl_sse2.h276 __m128i res0, res1, res2, res3, res4, res5, res6, res7; in FDCT8x8_2D() local
429 res7 = _mm_packs_epi32(w2, w3); in FDCT8x8_2D()
433 overflow = check_epi16_overflow_x4(&res1, &res7, &res5, &res3); in FDCT8x8_2D()
457 const __m128i tr0_5 = _mm_unpacklo_epi16(res6, res7); in FDCT8x8_2D()
459 const __m128i tr0_7 = _mm_unpackhi_epi16(res6, res7); in FDCT8x8_2D()
/external/clang/test/SemaCXX/
Daltivec.cpp26 int res7[vec_step(vus) == 8 ? 1 : -1]; in test_vec_step() local
/external/llvm-project/clang/test/SemaCXX/
Daltivec.cpp26 int res7[vec_step(vus) == 8 ? 1 : -1]; in test_vec_step() local
/external/llvm/test/CodeGen/ARM/
Dintrinsics-crypto.ll35 %res7 = call <4 x i32> @llvm.arm.neon.sha256h(<4 x i32> %res6, <4 x i32> %tmp3, <4 x i32> %res1)
37 %res8 = call <4 x i32> @llvm.arm.neon.sha256h2(<4 x i32> %res7, <4 x i32> %tmp3, <4 x i32> %res1)
/external/llvm-project/llvm/test/CodeGen/ARM/
Dintrinsics-crypto.ll35 %res7 = call <4 x i32> @llvm.arm.neon.sha256h(<4 x i32> %res6, <4 x i32> %tmp3, <4 x i32> %res1)
37 %res8 = call <4 x i32> @llvm.arm.neon.sha256h2(<4 x i32> %res7, <4 x i32> %tmp3, <4 x i32> %res1)
/external/llvm-project/clang/test/SemaOpenCL/
Dvec_step.cl22 int res7[vec_step(int2) == 2 ? 1 : -1];
/external/clang/test/SemaOpenCL/
Dvec_step.cl22 int res7[vec_step(int2) == 2 ? 1 : -1];
/external/ethtool/
Dfec_8xx.c37 uint32_t res7[3]; /* reserved */ member

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