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Searched refs:ret5 (Results 1 – 17 of 17) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/ARM/
Dfast-isel-ret.ll43 define zeroext i16 @ret5(i16 signext %a) nounwind uwtable ssp {
45 ; CHECK: ret5
/external/llvm/test/CodeGen/ARM/
Dfast-isel-ret.ll43 define zeroext i16 @ret5(i16 signext %a) nounwind uwtable ssp {
45 ; CHECK: ret5
/external/llvm-project/clang/test/CodeGen/
Dppc32-and-aix-struct-return.c76 Five ret5(void) { return (Five){"abcde"}; } in ret5() function
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dfast-isel-ret.ll59 define zeroext i16 @ret5(i16 signext %a) nounwind {
61 ; ELF64-LABEL: ret5
/external/llvm/test/CodeGen/PowerPC/
Dfast-isel-ret.ll63 define zeroext i16 @ret5(i16 signext %a) nounwind {
65 ; ELF64-LABEL: ret5
/external/llvm-project/llvm/test/CodeGen/SystemZ/
Dbswap-02.ll122 %ret5 = add i32 %ret4, %swapped5
123 %ret6 = add i32 %ret5, %swapped6
Dbswap-03.ll122 %ret5 = add i64 %ret4, %swapped5
123 %ret6 = add i64 %ret5, %swapped6
/external/llvm-project/llvm/test/CodeGen/X86/
Dvar-permute-256.ll127 %ret5 = insertelement <8 x i32> %ret4, i32 %v5, i32 5
128 %ret6 = insertelement <8 x i32> %ret5, i32 %v6, i32 6
251 %ret5 = insertelement <16 x i16> %ret4, i16 %v5, i32 5
252 %ret6 = insertelement <16 x i16> %ret5, i16 %v6, i32 6
404 %ret5 = insertelement <32 x i8> %ret4, i8 %v5, i32 5
405 %ret6 = insertelement <32 x i8> %ret5, i8 %v6, i32 6
547 %ret5 = insertelement <8 x float> %ret4, float %v5, i32 5
548 %ret6 = insertelement <8 x float> %ret5, float %v6, i32 6
799 %ret5 = insertelement <16 x i16> %ret4, i16 %v5, i32 5
800 %ret6 = insertelement <16 x i16> %ret5, i16 %v6, i32 6
[all …]
Dvar-permute-128.ll220 %ret5 = insertelement <8 x i16> %ret4, i16 %v5, i32 5
221 %ret6 = insertelement <8 x i16> %ret5, i16 %v6, i32 6
363 %ret5 = insertelement <16 x i8> %ret4, i8 %v5, i32 5
364 %ret6 = insertelement <16 x i8> %ret5, i8 %v6, i32 6
628 %ret5 = insertelement <16 x i8> %ret4, i8 %v5, i32 5
629 %ret6 = insertelement <16 x i8> %ret5, i8 %v6, i32 6
1091 %ret5 = insertelement <16 x i8> %ret4, i8 %v5, i32 5
1092 %ret6 = insertelement <16 x i8> %ret5, i8 %v6, i32 6
Dvar-permute-512.ll32 %ret5 = insertelement <8 x i64> %ret4, i64 %v5, i32 5
33 %ret6 = insertelement <8 x i64> %ret5, i64 %v6, i32 6
80 %ret5 = insertelement <16 x i32> %ret4, i32 %v5, i32 5
81 %ret6 = insertelement <16 x i32> %ret5, i32 %v6, i32 6
293 %ret5 = insertelement <32 x i16> %ret4, i16 %v5, i32 5
294 %ret6 = insertelement <32 x i16> %ret5, i16 %v6, i32 6
911 %ret5 = insertelement <64 x i8> %ret4, i8 %v5, i32 5
912 %ret6 = insertelement <64 x i8> %ret5, i8 %v6, i32 6
999 %ret5 = insertelement <8 x double> %ret4, double %v5, i32 5
1000 %ret6 = insertelement <8 x double> %ret5, double %v6, i32 6
[all …]
Davx512bw-intrinsics-upgrade.ll1935 %ret5 = add i64 %ret4, %res5
1937 %ret6 = add i64 %ret5, %res6
2054 %ret5 = add i64 %ret4, %res5
2056 %ret6 = add i64 %ret5, %res6
2147 %ret5 = add i64 %ret4, %res5
2149 %ret6 = add i64 %ret5, %res6
2266 %ret5 = add i64 %ret4, %res5
2268 %ret6 = add i64 %ret5, %res6
2330 %ret5 = add i32 %ret4, %res5
2332 %ret6 = add i32 %ret5, %res6
[all …]
/external/llvm/test/CodeGen/NVPTX/
Denvreg.ll111 %ret5 = add i32 %ret4, %val6
112 %ret6 = add i32 %ret5, %val7
/external/llvm-project/llvm/test/CodeGen/NVPTX/
Denvreg.ll111 %ret5 = add i32 %ret4, %val6
112 %ret6 = add i32 %ret5, %val7
/external/llvm/test/CodeGen/X86/
Davx512bw-intrinsics.ll82 %ret5 = add i64 %ret4, %res5
84 %ret6 = add i64 %ret5, %res6
171 %ret5 = add i64 %ret4, %res5
173 %ret6 = add i64 %ret5, %res6
258 %ret5 = add i64 %ret4, %res5
260 %ret6 = add i64 %ret5, %res6
347 %ret5 = add i64 %ret4, %res5
349 %ret6 = add i64 %ret5, %res6
421 %ret5 = add i32 %ret4, %res5
423 %ret6 = add i32 %ret5, %res6
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td17 list<SubRegIndex> ret5 = [sub0, sub1, sub2, sub3, sub4];
35 !if(!eq(size, 5), ret5,
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td59 list<SubRegIndex> ret5 = [sub0, sub1, sub2, sub3, sub4];
78 !if(!eq(size, 5), ret5,
/external/tensorflow/tensorflow/python/kernel_tests/
Dwhile_v2_test.py568 ret5 = while_loop_v2(
573 return ret1, ret2, ret3, ret4, ret5