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Searched refs:s_load_dwordx8 (Results 1 – 25 of 57) sorted by relevance

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/external/llvm/test/MC/AMDGPU/
Dout-of-range-registers.s40 s_load_dwordx8 s[104:111], s[2:3], s4 label
43 s_load_dwordx8 s[100:107], s[2:3], s4 label
46 s_load_dwordx8 s[108:115], s[2:3], s4 label
Dsmrd.s63 s_load_dwordx8 s[8:15], s[2:3], 1 label
67 s_load_dwordx8 s[8:15], s[2:3], s4 label
71 s_load_dwordx8 s[96:103], s[2:3], s4 label
Dsmrd-err.s9 s_load_dwordx8 s[96:103], s[2:3], s4 label
/external/llvm-project/llvm/test/MC/AMDGPU/
Dout-of-range-registers.s62 s_load_dwordx8 s[104:111], s[2:3], s4 label
65 s_load_dwordx8 s[100:107], s[2:3], s4 label
68 s_load_dwordx8 s[108:115], s[2:3], s4 label
Dtrap.s211 s_load_dwordx8 ttmp[0:7], s[0:1], s0 label
216 s_load_dwordx8 ttmp[4:11], s[0:1], s0 label
221 s_load_dwordx8 ttmp[8:15], s[0:1], s0 label
Dsmrd.s110 s_load_dwordx8 s[8:15], s[2:3], 1 label
114 s_load_dwordx8 s[8:15], s[2:3], s4 label
118 s_load_dwordx8 s[96:103], s[2:3], s4 label
Dsmrd-err.s8 s_load_dwordx8 s[96:103], s[2:3], s4 label
Dsym_kernel_scope.s33 s_load_dwordx8 s[16:23], s[0:1], 0x0
/external/llvm/test/CodeGen/AMDGPU/
Dinline-constraints.ll11 ; GCN: s_load_dwordx8 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]
21 …%s256 = tail call <8 x i32> asm sideeffect "s_load_dwordx8 $0, $1", "=s,s"(i32 addrspace(1)* %ptr)
Dload-constant-i64.ll28 ; GCN: s_load_dwordx8 {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x0{{$}}
40 ; GCN: s_load_dwordx8
Dload-constant-i32.ll51 ; GCN: s_load_dwordx8
183 ; GCN: s_load_dwordx8
202 ; GCN: s_load_dwordx8
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dsaddo.ll158 ; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
188 ; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
212 ; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
238 ; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
265 ; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
287 ; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
314 ; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
345 ; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
370 ; GFX9-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x24
398 ; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
[all …]
Dconstant-address-space-32bit.ll61 ; SICI-DAG: s_load_dwordx8 s[{{.*}}], s[0:1], 0x0
62 ; SICI-DAG: s_load_dwordx8 s[{{.*}}], s[2:3], 0x10
63 ; VIGFX9-DAG: s_load_dwordx8 s[{{.*}}], s[0:1], 0x0
64 ; VIGFX9-DAG: s_load_dwordx8 s[{{.*}}], s[2:3], 0x40
143 ; SICI-DAG: s_load_dwordx8 s[{{.*}}], s[0:1], 0x0
144 ; SICI-DAG: s_load_dwordx8 s[{{.*}}], s[2:3], 0x10
145 ; VIGFX9-DAG: s_load_dwordx8 s[{{.*}}], s[0:1], 0x0
146 ; VIGFX9-DAG: s_load_dwordx8 s[{{.*}}], s[2:3], 0x40
207 ; GCN: s_load_dwordx8
241 ; GCN: s_load_dwordx8
Dselect.f16.ll8 ; SI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x9
49 ; VI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x24
99 ; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
134 ; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
178 ; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
213 ; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
257 ; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
292 ; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
337 ; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
372 ; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
[all …]
Dload-constant-i64.ll28 ; GCN: s_load_dwordx8 {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x0{{$}}
40 ; GCN: s_load_dwordx8
Dkernel-args.ll457 ; SI-DAG: s_load_dwordx8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x19
459 ; MESA-VI-DAG: s_load_dwordx8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x64
461 ; HSA-GFX9-DAG: s_load_dwordx8 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x40
482 ; SI-DAG: s_load_dwordx8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x19
484 ; MESA-VI-DAG: s_load_dwordx8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x64
486 ; HSA-GFX9-DAG: s_load_dwordx8 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x40
561 ; SI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x11
562 ; MESA-VI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x44
563 ; HSA-GFX9: s_load_dwordx8 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x20
581 ; SI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x11
[all …]
Dshift-i128.ll187 ; GCN-NEXT: s_load_dwordx8 s[4:11], s[4:5], 0x0
224 ; GCN-NEXT: s_load_dwordx8 s[4:11], s[4:5], 0x0
261 ; GCN-NEXT: s_load_dwordx8 s[4:11], s[4:5], 0x0
449 ; GCN-NEXT: s_load_dwordx8 s[16:23], s[4:5], 0x8
450 ; GCN-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
519 ; GCN-NEXT: s_load_dwordx8 s[16:23], s[4:5], 0x8
520 ; GCN-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
589 ; GCN-NEXT: s_load_dwordx8 s[16:23], s[4:5], 0x8
590 ; GCN-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
Dload-constant-f32.ll6 ; GCN: s_load_dwordx8
Dv_madak_f16.ll70 ; SI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x9
109 ; VI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x24
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dfmed3.ll9 ; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
31 ; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
62 ; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
94 ; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
126 ; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
167 ; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
209 ; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
233 ; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
266 ; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
306 ; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
[all …]
Dinst-select-load-smrd.mir173 ; CHECK: s_load_dwordx8 [[CONSTANT_PTR]]
181 ; CHECK: s_load_dwordx8 [[GLOBAL_PTR]]
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
Dtrap_gfx9.txt124 # GFX9: s_load_dwordx8 ttmp[0:7], s[0:1], s0 ; encoding: [0x00,0x1b,0x0c,0xc0,0x00,0x00,0x00,0x00]
127 # GFX9: s_load_dwordx8 ttmp[4:11], s[0:1], s0 ; encoding: [0x00,0x1c,0x0c,0xc0,0x00,0x00,0x00,0x0…
130 # GFX9: s_load_dwordx8 ttmp[8:15], s[0:1], s0 ; encoding: [0x00,0x1d,0x0c,0xc0,0x00,0x00,0x00,0x0…
Dsmrd_vi.txt30 # VI: s_load_dwordx8 s[8:15], s[2:3], 0x1 ; encoding: [0x01,0x02,0x0e,0xc0,0x01,0x00,0x00,0x00]
33 # VI: s_load_dwordx8 s[8:15], s[2:3], s4 ; encoding: [0x01,0x02,0x0c,0xc0,0x04,0x00,0x00,0x00]
Dtrap_vi.txt121 # VI: s_load_dwordx8 ttmp[0:7], s[0:1], s0 ; encoding: [0x00,0x1c,0x0c,0xc0,0x00,0x00,0x00,0x00]
124 # VI: s_load_dwordx8 ttmp[4:11], s[0:1], s0 ; encoding: [0x00,0x1d,0x0c,0xc0,0x00,0x00,0x00,0x00]
/external/llvm/test/MC/Disassembler/AMDGPU/
Dsmrd_vi.txt27 # VI: s_load_dwordx8 s[8:15], s[2:3], 0x1 ; encoding: [0x01,0x02,0x0e,0xc0,0x01,0x00,0x00,0x00]
30 # VI: s_load_dwordx8 s[8:15], s[2:3], s4 ; encoding: [0x01,0x02,0x0c,0xc0,0x04,0x00,0x00,0x00]

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