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Searched refs:samples_log2 (Results 1 – 6 of 6) sorted by relevance

/external/mesa3d/src/amd/vulkan/
Dradv_meta_decompress.c348 uint32_t samples_log2 = ffs(samples) - 1; in radv_get_depth_pipeline() local
360 if (!state->depth_decomp[samples_log2].decompress_pipeline[decompress]) { in radv_get_depth_pipeline()
365 state->depth_decomp[samples_log2].pass, in radv_get_depth_pipeline()
366 state->depth_decomp[samples_log2].p_layout, in radv_get_depth_pipeline()
369 &state->depth_decomp[samples_log2].decompress_pipeline[i]); in radv_get_depth_pipeline()
377 state->depth_decomp[samples_log2].pass, in radv_get_depth_pipeline()
378 state->depth_decomp[samples_log2].p_layout, in radv_get_depth_pipeline()
381 &state->depth_decomp[samples_log2].resummarize_pipeline); in radv_get_depth_pipeline()
390 pipeline = &state->depth_decomp[samples_log2].decompress_pipeline[decompress]; in radv_get_depth_pipeline()
393 pipeline = &state->depth_decomp[samples_log2].resummarize_pipeline; in radv_get_depth_pipeline()
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Dradv_meta_resolve_fs.c157 int samples_log2, in create_resolve_pipeline() argument
163 VkPipeline *pipeline = &device->meta_state.resolve_fragment.rc[samples_log2].pipeline[fs_key]; in create_resolve_pipeline()
171 uint32_t samples = 1 << samples_log2; in create_resolve_pipeline()
183 VkRenderPass *rp = &device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key][0]; in create_resolve_pipeline()
475 int samples_log2, in create_depth_stencil_resolve_pipeline() argument
495 pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].average_pipeline; in create_depth_stencil_resolve_pipeline()
499 pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].min_pipeline; in create_depth_stencil_resolve_pipeline()
501 pipeline = &device->meta_state.resolve_fragment.stencil[samples_log2].min_pipeline; in create_depth_stencil_resolve_pipeline()
505 pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].max_pipeline; in create_depth_stencil_resolve_pipeline()
507 pipeline = &device->meta_state.resolve_fragment.stencil[samples_log2].max_pipeline; in create_depth_stencil_resolve_pipeline()
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Dradv_meta_clear.c407 uint32_t samples, samples_log2; in emit_color_clear() local
426 samples_log2 = ffs(samples) - 1; in emit_color_clear()
434 if (device->meta_state.clear[samples_log2].render_pass[fs_key] == VK_NULL_HANDLE) { in emit_color_clear()
437 … &device->meta_state.clear[samples_log2].render_pass[fs_key]); in emit_color_clear()
444 if (device->meta_state.clear[samples_log2].color_pipelines[fs_key] == VK_NULL_HANDLE) { in emit_color_clear()
446 … &device->meta_state.clear[samples_log2].color_pipelines[fs_key], in emit_color_clear()
447 device->meta_state.clear[samples_log2].render_pass[fs_key]); in emit_color_clear()
454 pipeline = device->meta_state.clear[samples_log2].color_pipelines[fs_key]; in emit_color_clear()
459 assert(samples_log2 < ARRAY_SIZE(device->meta_state.clear)); in emit_color_clear()
746 int samples_log2, in pick_depthstencil_pipeline() argument
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Dradv_meta_resolve_cs.c609 uint32_t samples_log2 = ffs(samples) - 1; in radv_get_resolve_pipeline() local
613 pipeline = &state->resolve_compute.rc[samples_log2].i_pipeline; in radv_get_resolve_pipeline()
615 pipeline = &state->resolve_compute.rc[samples_log2].srgb_pipeline; in radv_get_resolve_pipeline()
617 pipeline = &state->resolve_compute.rc[samples_log2].pipeline; in radv_get_resolve_pipeline()
712 const uint32_t samples_log2 = ffs(samples) - 1; in emit_depth_stencil_resolve() local
759 pipeline = &device->meta_state.resolve_compute.depth[samples_log2].average_pipeline; in emit_depth_stencil_resolve()
763 pipeline = &device->meta_state.resolve_compute.depth[samples_log2].min_pipeline; in emit_depth_stencil_resolve()
765 pipeline = &device->meta_state.resolve_compute.stencil[samples_log2].min_pipeline; in emit_depth_stencil_resolve()
769 pipeline = &device->meta_state.resolve_compute.depth[samples_log2].max_pipeline; in emit_depth_stencil_resolve()
771 pipeline = &device->meta_state.resolve_compute.stencil[samples_log2].max_pipeline; in emit_depth_stencil_resolve()
Dradv_meta_fmask_expand.c119 const uint32_t samples_log2 = ffs(samples) - 1; in radv_expand_fmask_image_inplace() local
125 VkPipeline pipeline = device->meta_state.fmask_expand.pipeline[samples_log2]; in radv_expand_fmask_image_inplace()
/external/mesa3d/src/amd/compiler/
Daco_instruction_selection.cpp8735 …Temp samples_log2 = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand… in visit_tex() local
8736 …mples = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), Operand(1u), samples_log2); in visit_tex()