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/external/mesa3d/src/intel/compiler/
Dbrw_fs_nir.cpp4851 fs_reg size_padding = ubld.vgrf(BRW_REGISTER_TYPE_UD); in nir_emit_intrinsic() local
4854 ubld.AND(size_padding, ret_payload, brw_imm_ud(3)); in nir_emit_intrinsic()
4856 ubld.ADD(buffer_size, size_aligned4, negate(size_padding)); in nir_emit_intrinsic()