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Searched refs:snez (Results 1 – 12 of 12) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/RISCV/
Dumulo-128-legalisation-lowering.ll66 ; RISCV32-NEXT: snez a1, s8
67 ; RISCV32-NEXT: snez a3, s3
70 ; RISCV32-NEXT: snez a3, a3
73 ; RISCV32-NEXT: snez a3, a3
77 ; RISCV32-NEXT: snez a3, s5
78 ; RISCV32-NEXT: snez a4, s2
81 ; RISCV32-NEXT: snez a4, a4
84 ; RISCV32-NEXT: snez a4, a4
88 ; RISCV32-NEXT: snez a3, a3
90 ; RISCV32-NEXT: snez a4, a4
Dsetcc-logic.ll37 ; RV32I-NEXT: snez a0, a0
47 ; RV64I-NEXT: snez a0, a0
84 ; RV32I-NEXT: snez a0, a0
94 ; RV64I-NEXT: snez a0, a0
106 ; RV32I-NEXT: snez a1, a1
108 ; RV32I-NEXT: snez a0, a0
117 ; RV64I-NEXT: snez a1, a1
119 ; RV64I-NEXT: snez a0, a0
Di32-icmp.ll5 ; TODO: check the generated instructions for the equivalent of seqz, snez,
78 ; RV32I-NEXT: snez a0, a0
89 ; RV32I-NEXT: snez a0, a0
100 ; RV32I-NEXT: snez a0, a0
112 ; RV32I-NEXT: snez a0, a0
122 ; RV32I-NEXT: snez a0, a0
Dsext-zext-trunc.ll482 ; RV32I-NEXT: snez a0, a0
491 ; RV64I-NEXT: snez a0, a0
505 ; RV32I-NEXT: snez a0, a0
513 ; RV64I-NEXT: snez a0, a0
Dfp128.ll37 ; RV32I-NEXT: snez a0, a0
Drv32Zbb.ll1230 ; RV32I-NEXT: snez a2, a0
1241 ; RV32IB-NEXT: snez a2, a0
1252 ; RV32IBB-NEXT: snez a2, a0
Dmul.ll533 ; RV32I-NEXT: snez a1, a3
Drv64i-single-softfloat.ll163 ; RV64I-NEXT: snez a0, a0
/external/llvm-project/llvm/test/MC/RISCV/
Drvi-aliases-valid.s56 # CHECK-S-OBJ: snez t6, ra
57 snez x31, x1 label
/external/elfutils/tests/
Dtestfile-riscv64-dis1.expect.bz2 ... tp,a6 101 180: 33 30 00 00 snez zero,zero 102 184: b3 30 00 01 ...
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfo.td600 def : InstAlias<"snez $rd, $rs", (SLTU GPR:$rd, X0, GPR:$rs)>;
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfo.td662 def : InstAlias<"snez $rd, $rs", (SLTU GPR:$rd, X0, GPR:$rs)>;