| /external/mesa3d/src/gallium/drivers/etnaviv/ |
| D | etnaviv_disasm.c | 57 uint32_t src0_neg : 1; member
555 .neg = instr->src0_neg, in print_instr()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600InstrFormats.td | 96 bits<1> src0_neg;
99 let Word0{12} = src0_neg;
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| D | R600Instructions.td | 97 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
102 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
139 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
145 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
179 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
185 "$src0_neg$src0$src0_rel, "
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| D | R600ExpandSpecialInstrs.cpp | 342 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src0_neg); in runOnMachineFunction()
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| D | VIInstrFormats.td | 200 let Inst{52} = src0_modifiers{0}; // src0_neg
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| D | R600InstrInfo.cpp | 1322 OPERAND_CASE(AMDGPU::OpName::src0_neg) in getSlotedOps()
1362 AMDGPU::OpName::src0_neg, in buildSlotOfVectorInstruction()
1451 FlagIndex = getOperandIdx(MI, AMDGPU::OpName::src0_neg); in getFlagOp()
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| D | EvergreenInstructions.td | 405 let src0_neg = 0;
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| D | R600ISelLowering.cpp | 2387 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg), in PostISelFolding()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | R600InstrFormats.td | 105 bits<1> src0_neg;
108 let Word0{12} = src0_neg;
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| D | R600ExpandSpecialInstrs.cpp | 278 SetFlagInNewMI(NewMI, &MI, R600::OpName::src0_neg); in runOnMachineFunction()
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| D | R600Instructions.td | 107 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
112 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
149 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
155 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
189 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
195 "$src0_neg$src0$src0_rel, "
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| D | R600InstrInfo.cpp | 1300 OPERAND_CASE(R600::OpName::src0_neg) in getSlotedOps()
1340 R600::OpName::src0_neg, in buildSlotOfVectorInstruction()
1425 FlagIndex = getOperandIdx(MI, R600::OpName::src0_neg); in getFlagOp()
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| D | VOPInstructions.td | 596 let Inst{52} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // src0_neg
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| D | EvergreenInstructions.td | 590 let src0_neg = 0;
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| D | R600ISelLowering.cpp | 2277 TII->getOperandIdx(Opcode, R600::OpName::src0_neg), in PostISelFolding()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600InstrFormats.td | 105 bits<1> src0_neg;
108 let Word0{12} = src0_neg;
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| D | R600ExpandSpecialInstrs.cpp | 278 SetFlagInNewMI(NewMI, &MI, R600::OpName::src0_neg); in runOnMachineFunction()
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| D | R600Instructions.td | 107 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
112 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
149 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
155 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
189 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
195 "$src0_neg$src0$src0_rel, "
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| D | R600InstrInfo.cpp | 1299 OPERAND_CASE(R600::OpName::src0_neg) in getSlotedOps()
1339 R600::OpName::src0_neg, in buildSlotOfVectorInstruction()
1424 FlagIndex = getOperandIdx(MI, R600::OpName::src0_neg); in getFlagOp()
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| D | EvergreenInstructions.td | 479 let src0_neg = 0;
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| D | VOPInstructions.td | 586 let Inst{52} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // src0_neg
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| D | R600ISelLowering.cpp | 2272 TII->getOperandIdx(Opcode, R600::OpName::src0_neg), in PostISelFolding()
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| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| D | radeon_optimize.c | 584 unsigned src0_neg = inst_add->U.I.SrcReg[0].Negate & dstmask; in peephole_add_presub_add() local
599 if (inst_add->U.I.SrcReg[0].Negate && src0_neg != dstmask) in peephole_add_presub_add()
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