| /external/tremolo/Tremolo/ |
| D | bitwiseARM.s | 140 @ stall
141 @ stall
144 @ stall
145 @ stall
152 @ stall
153 @ stall
182 @ stall
187 @ stall
328 @ stall
346 @ stall
[all …]
|
| D | dpen.s | 109 @ stall Xscale
134 @ stall Xscale
151 @ stall Xscale
166 @ stall Xscale
192 @ stall Xscale
211 @ stall Xscale
224 @ stall Xscale
485 @ stall
486 @ stall Xscale
490 @ stall Xscale
|
| D | mdctLARM.s | 103 @ stall
104 @ stall (Xscale)
171 @ stall
172 @ stall (Xscale)
492 @ stall Xscale
558 @ stall Xscale
581 @ stall Xscale
635 @ stall Xscale
710 @ stall Xscale
1004 @ stall XScale
|
| /external/mesa3d/src/mesa/sparc/ |
| D | norm.S | 73 fadds %f5, %f0, %f5 ! FGA Group stall f0,f5 available
74 fadds %f7, %f4, %f7 ! FGA Group stall f4,f7 available
82 fadds %f6, %f8, %f6 ! FGA Group 2cyc stall f6,f8 available
83 fadds %f6, %f10, %f6 ! FGA Group 4cyc stall f6,f10 available
139 fadds %f5, %f0, %f5 ! FGA Group stall f0,f5 available
141 fadds %f7, %f4, %f7 ! FGA Group stall f4,f7 available
206 fmuls %f3, %f3, %f6 ! FGM Group stall, f3 available
209 fadds %f6, %f8, %f6 ! FGA Group 2cyc stall f6,f8 available
210 fadds %f6, %f10, %f6 ! FGA Group 4cyc stall f6,f10 available
372 fadds %f5, %f0, %f5 ! FGA Group stall f0,f5 available
[all …]
|
| D | xform.S | 82 fmuls %f0, M0, %f1 ! FGM Group 1-cycle stall on %f0
115 fmuls %f0, M0, %f1 ! FGM Group 1-cycle stall on %f0
253 fadds %f1, M12, %f3 ! FGA Group, 2 cycle stall, f1 available
364 fadds %f1, M12, %f1 ! FGA Group, 2 cycle stall, f1 available
577 fadds %f2, %f6, %f2 ! FGA Group 2 cycle stall, f2 available
634 fadds %f2, M12, %f2 ! FGA Group, 2 cycle stall, f2 available
718 fadds %f2, %f6, %f2 ! FGA Group stall, f2, f6, f7 available
779 fadds %f2, M12, %f2 ! FGA Group, 2 cycle stall, f2 available
1007 fadds %f5, %f11, %f5 ! FGA Group stall, f11, f5 available
1044 fadds %f3, M12, %f3 ! FGA Group, stall, f3 available
[all …]
|
| D | sparc_clip.S | 119 cmp %g3, 0 ! IEU1 Group, stall
205 cmp %g3, 0 ! IEU1 Group, stall
|
| /external/libdrm/intel/tests/ |
| D | gen6-3d.batch-ref.txt | 2 0x12300004: 0x00100002: no write, cs stall, stall at scoreboard,
71 0x12300118: 0x00002804: no write, depth stall, instruction cache invalidate, state cache in…
131 0x12300208: 0x00002000: no write, depth stall,
139 0x12300228: 0x00002000: no write, depth stall,
198 0x12300314: 0x00100002: no write, cs stall, stall at scoreboard,
206 0x12300334: 0x00002804: no write, depth stall, instruction cache invalidate, state cache in…
280 0x1230045c: 0x00100002: no write, cs stall, stall at scoreboard,
288 0x1230047c: 0x00002804: no write, depth stall, instruction cache invalidate, state cache in…
332 0x1230052c: 0x00100002: no write, cs stall, stall at scoreboard,
340 0x1230054c: 0x00002804: no write, depth stall, instruction cache invalidate, state cache in…
[all …]
|
| D | gen7-3d.batch-ref.txt | 164 0x1230028c: 0x00002000: no write, depth stall,
172 0x123002ac: 0x00002000: no write, depth stall,
|
| /external/mesa3d/docs/relnotes/ |
| D | 18.0.4.rst | 77 - i965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROL
108 - i965: require pixel scoreboard stall prior to ISP disable
109 - anv: emit pixel scoreboard stall before ISP disable
|
| D | 20.0.2.rst | 102 - anv: Use the PIPE_CONTROL instead of bits for the CS stall W/A
103 - anv: Use a proper end-of-pipe sync instead of just CS stall
104 - anv: Do end-of-pipe sync around MCS/CCS ops instead of CS stall
|
| D | 13.0.2.rst | 112 - anv: Implement a depth stall restriction on gen7
115 - anv/cmd_buffer: Emit a CS stall before setting a CS pipeline
|
| /external/rust/crates/quiche/deps/boringssl/linux-arm/crypto/fipsmodule/ |
| D | sha1-armv4-large.S | 220 eor r11,r11,r12 @ 1 cycle stall
237 eor r11,r11,r12 @ 1 cycle stall
254 eor r11,r11,r12 @ 1 cycle stall
271 eor r11,r11,r12 @ 1 cycle stall
292 eor r11,r11,r12 @ 1 cycle stall
308 eor r11,r11,r12 @ 1 cycle stall
324 eor r11,r11,r12 @ 1 cycle stall
340 eor r11,r11,r12 @ 1 cycle stall
356 eor r11,r11,r12 @ 1 cycle stall
384 eor r11,r11,r12 @ 1 cycle stall
[all …]
|
| /external/boringssl/linux-arm/crypto/fipsmodule/ |
| D | sha1-armv4-large.S | 220 eor r11,r11,r12 @ 1 cycle stall
237 eor r11,r11,r12 @ 1 cycle stall
254 eor r11,r11,r12 @ 1 cycle stall
271 eor r11,r11,r12 @ 1 cycle stall
292 eor r11,r11,r12 @ 1 cycle stall
308 eor r11,r11,r12 @ 1 cycle stall
324 eor r11,r11,r12 @ 1 cycle stall
340 eor r11,r11,r12 @ 1 cycle stall
356 eor r11,r11,r12 @ 1 cycle stall
384 eor r11,r11,r12 @ 1 cycle stall
[all …]
|
| /external/rust/crates/quiche/deps/boringssl/ios-arm/crypto/fipsmodule/ |
| D | sha1-armv4-large.S | 221 eor r11,r11,r12 @ 1 cycle stall
238 eor r11,r11,r12 @ 1 cycle stall
255 eor r11,r11,r12 @ 1 cycle stall
272 eor r11,r11,r12 @ 1 cycle stall
293 eor r11,r11,r12 @ 1 cycle stall
309 eor r11,r11,r12 @ 1 cycle stall
325 eor r11,r11,r12 @ 1 cycle stall
341 eor r11,r11,r12 @ 1 cycle stall
357 eor r11,r11,r12 @ 1 cycle stall
385 eor r11,r11,r12 @ 1 cycle stall
[all …]
|
| /external/openscreen/third_party/boringssl/ios-arm/crypto/fipsmodule/ |
| D | sha1-armv4-large.S | 221 eor r11,r11,r12 @ 1 cycle stall
238 eor r11,r11,r12 @ 1 cycle stall
255 eor r11,r11,r12 @ 1 cycle stall
272 eor r11,r11,r12 @ 1 cycle stall
293 eor r11,r11,r12 @ 1 cycle stall
309 eor r11,r11,r12 @ 1 cycle stall
325 eor r11,r11,r12 @ 1 cycle stall
341 eor r11,r11,r12 @ 1 cycle stall
357 eor r11,r11,r12 @ 1 cycle stall
385 eor r11,r11,r12 @ 1 cycle stall
[all …]
|
| /external/openscreen/third_party/boringssl/linux-arm/crypto/fipsmodule/ |
| D | sha1-armv4-large.S | 220 eor r11,r11,r12 @ 1 cycle stall
237 eor r11,r11,r12 @ 1 cycle stall
254 eor r11,r11,r12 @ 1 cycle stall
271 eor r11,r11,r12 @ 1 cycle stall
292 eor r11,r11,r12 @ 1 cycle stall
308 eor r11,r11,r12 @ 1 cycle stall
324 eor r11,r11,r12 @ 1 cycle stall
340 eor r11,r11,r12 @ 1 cycle stall
356 eor r11,r11,r12 @ 1 cycle stall
384 eor r11,r11,r12 @ 1 cycle stall
[all …]
|
| /external/boringssl/ios-arm/crypto/fipsmodule/ |
| D | sha1-armv4-large.S | 221 eor r11,r11,r12 @ 1 cycle stall
238 eor r11,r11,r12 @ 1 cycle stall
255 eor r11,r11,r12 @ 1 cycle stall
272 eor r11,r11,r12 @ 1 cycle stall
293 eor r11,r11,r12 @ 1 cycle stall
309 eor r11,r11,r12 @ 1 cycle stall
325 eor r11,r11,r12 @ 1 cycle stall
341 eor r11,r11,r12 @ 1 cycle stall
357 eor r11,r11,r12 @ 1 cycle stall
385 eor r11,r11,r12 @ 1 cycle stall
[all …]
|
| /external/llvm-project/llvm/test/tools/llvm-mca/X86/Barcelona/ |
| D | partial-reg-update-5.s | 4 lzcnt %ax, %bx ## partial register stall.
|
| /external/llvm-project/llvm/test/tools/llvm-mca/X86/BtVer2/ |
| D | partial-reg-update-5.s | 6 lzcnt %ax, %bx ## partial register stall.
|
| /external/llvm-project/llvm/test/tools/llvm-mca/X86/Znver2/ |
| D | partial-reg-update-5.s | 4 lzcnt %ax, %bx ## partial register stall.
|
| /external/llvm-project/llvm/test/tools/llvm-mca/X86/Znver1/ |
| D | partial-reg-update-5.s | 4 lzcnt %ax, %bx ## partial register stall.
|
| /external/llvm-project/llvm/test/tools/llvm-mca/X86/BdVer2/ |
| D | partial-reg-update-5.s | 6 lzcnt %ax, %bx ## partial register stall.
|
| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | regbank-reassign-wave64.mir | 5 # conflicts. If this is mishandled stall counts will be incorrect and cause an
|
| /external/igt-gpu-tools/tools/ |
| D | intel_reg_decode.c | 642 const char *stall; in DEBUGSTRING() local
648 stall = "no stall"; in DEBUGSTRING()
651 stall = "stall"; in DEBUGSTRING()
654 stall = "TV stall"; in DEBUGSTRING()
657 stall = "unknown stall"; in DEBUGSTRING()
662 enable, disp_pipe, stall, hsync, vsync); in DEBUGSTRING()
669 const char *stall = val & SDVO_STALL_SELECT ? "enabled" : "disabled"; in DEBUGSTRING() local
683 enable, disp_pipe, stall, detected, sdvoextra, gang); in DEBUGSTRING()
|
| /external/llvm/test/CodeGen/X86/ |
| D | 3addr-16bit.ll | 4 ; In 32-bit the partial register stall would degrade performance.
|