| /external/llvm/test/MC/ARM/ |
| D | load-store-acquire-release-v8-thumb.s | 17 stlexb r1, r3, [r4]
21 @ CHECK: stlexb r1, r3, [r4] @ encoding: [0xc4,0xe8,0xc1,0x3f]
|
| D | load-store-acquire-release-v8.s | 17 stlexb r1, r3, [r4]
21 @ CHECK: stlexb r1, r3, [r4] @ encoding: [0x93,0x1e,0xc4,0xe1]
|
| D | thumbv8m.s | 133 stlexb r1, r2, [r3] label
|
| /external/llvm-project/llvm/test/MC/ARM/ |
| D | load-store-acquire-release-v8-thumb.s | 17 stlexb r1, r3, [r4]
21 @ CHECK: stlexb r1, r3, [r4] @ encoding: [0xc4,0xe8,0xc1,0x3f]
|
| D | load-store-acquire-release-v8.s | 17 stlexb r1, r3, [r4]
21 @ CHECK: stlexb r1, r3, [r4] @ encoding: [0x93,0x1e,0xc4,0xe1]
|
| D | thumbv8m.s | 133 stlexb r1, r2, [r3] label
|
| /external/capstone/suite/MC/ARM/ |
| D | load-store-acquire-release-v8.s.cs | 6 0x93,0x1e,0xc4,0xe1 = stlexb r1, r3, [r4]
|
| D | load-store-acquire-release-v8-thumb.s.cs | 6 0xc4,0xe8,0xc1,0x3f = stlexb r1, r3, [r4]
|
| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | load-store-acquire-release-v8.txt | 15 # CHECK: stlexb r1, r3, [r4] @ encoding: [0x93,0x1e,0xc4,0xe1]
|
| D | load-store-acquire-release-v8-thumb.txt | 16 # CHECK: stlexb r1, r3, [r4] @ encoding: [0xc4,0xe8,0xc1,0x3f]
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | load-store-acquire-release-v8-thumb.txt | 16 # CHECK: stlexb r1, r3, [r4] @ encoding: [0xc4,0xe8,0xc1,0x3f]
|
| D | load-store-acquire-release-v8.txt | 15 # CHECK: stlexb r1, r3, [r4] @ encoding: [0x93,0x1e,0xc4,0xe1]
|
| /external/llvm/test/CodeGen/ARM/ |
| D | ldaex-stlex.ll | 67 ; CHECK: stlexb r0, r1, [r2]
|
| D | atomic-ops-v8.ll | 24 ; CHECK-NEXT: stlexb [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
216 ; CHECK-NEXT: stlexb [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
312 ; CHECK-NEXT: stlexb [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
709 ; CHECK-NEXT: stlexb [[STATUS:r[0-9]+]], r[[OLDX]], {{.*}}[[ADDR]]
935 ; CHECK-NEXT: stlexb [[STATUS:r[0-9]+]], r[[NEW]], {{.*}}[[ADDR]]
|
| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | ldaex-stlex.ll | 67 ; CHECK: stlexb r0, r1, [r2]
|
| D | atomic-ops-m33.ll | 16 ; CHECK-NEXT: stlexb [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
|
| D | atomic-ops-v8.ll | 24 ; CHECK-NEXT: stlexb [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
216 ; CHECK-NEXT: stlexb [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
312 ; CHECK-NEXT: stlexb [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
709 ; CHECK-NEXT: stlexb [[STATUS:r[0-9]+]], r[[OLDX]], {{.*}}[[ADDR]]
935 ; CHECK-NEXT: stlexb [[STATUS:r[0-9]+]], r[[NEW]], {{.*}}[[ADDR]]
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3276 void stlexb(Condition cond,
3280 void stlexb(Register rd, Register rt, const MemOperand& operand) { in stlexb() function
3281 stlexb(al, rd, rt, operand); in stlexb()
|
| D | disasm-aarch32.h | 1206 void stlexb(Condition cond,
|
| /external/capstone/arch/AArch64/ |
| D | ARMMappingInsnOp.inc | 943 { /* ARM_STLEXB, ARM_INS_STLEXB: stlexb${p} $rd, $rt, $addr */
6157 { /* ARM_t2STLEXB, ARM_INS_STLEXB: stlexb${p} $rd, $rt, $addr */
|
| /external/capstone/arch/ARM/ |
| D | ARMMappingInsnOp.inc | 943 { /* ARM_STLEXB, ARM_INS_STLEXB: stlexb${p} $rd, $rt, $addr */
6157 { /* ARM_t2STLEXB, ARM_INS_STLEXB: stlexb${p} $rd, $rt, $addr */
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 3395 "stlexb", "\t$Rd, $Rt, $addr", "",
|
| D | ARMInstrInfo.td | 4734 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr",
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 3618 "stlexb", "\t$Rd, $Rt, $addr", "",
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 3687 "stlexb", "\t$Rd, $Rt, $addr", "",
|