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Searched refs:tegra_mc_write_32 (Results 1 – 7 of 7) sorted by relevance

/external/arm-trusted-firmware/plat/nvidia/tegra/drivers/memctrl/
Dmemctrl_v1.c37 tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_0_0, in tegra_memctrl_setup()
39 tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_1_0, in tegra_memctrl_setup()
41 tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_2_0, in tegra_memctrl_setup()
43 tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_3_0, in tegra_memctrl_setup()
45 tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_4_0, in tegra_memctrl_setup()
48 tegra_mc_write_32(MC_SMMU_ASID_SECURITY_0, MC_SMMU_ASID_SECURITY); in tegra_memctrl_setup()
50 tegra_mc_write_32(MC_SMMU_TLB_CONFIG_0, MC_SMMU_TLB_CONFIG_0_RESET_VAL); in tegra_memctrl_setup()
51 tegra_mc_write_32(MC_SMMU_PTC_CONFIG_0, MC_SMMU_PTC_CONFIG_0_RESET_VAL); in tegra_memctrl_setup()
54 tegra_mc_write_32(MC_SMMU_PTC_FLUSH_0, MC_SMMU_PTC_FLUSH_ALL); in tegra_memctrl_setup()
56 tegra_mc_write_32(MC_SMMU_TLB_FLUSH_0, MC_SMMU_TLB_FLUSH_ALL); in tegra_memctrl_setup()
[all …]
Dmemctrl_v2.c56 tegra_mc_write_32(MC_SMMU_BYPASS_CONFIG, in tegra_memctrl_setup()
70 tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, in tegra_memctrl_restore_settings()
74 tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, in tegra_memctrl_restore_settings()
78 tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, in tegra_memctrl_restore_settings()
186 tegra_mc_write_32(index, 0); in tegra_lock_videomem_nonoverlap()
193 tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_LO, (uint32_t)phys_base); in tegra_lock_videomem_nonoverlap()
194 tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_HI, in tegra_lock_videomem_nonoverlap()
206 tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_SIZE, (uint32_t)val); in tegra_lock_videomem_nonoverlap()
213 tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_CFG, in tegra_lock_videomem_nonoverlap()
225 tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_LO, 0); in tegra_unlock_videomem_nonoverlap()
[all …]
/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t194/
Dplat_memctrl.c73 tegra_mc_write_32(MC_SECURITY_CFG0_0, phys_base_lo); in plat_memctrl_tzdram_setup()
74 tegra_mc_write_32(MC_SECURITY_CFG3_0, phys_base_hi); in plat_memctrl_tzdram_setup()
75 tegra_mc_write_32(MC_SECURITY_CFG1_0, (uint32_t)(size_in_bytes >> 20)); in plat_memctrl_tzdram_setup()
/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t186/
Dplat_memctrl.c167 tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0); in tegra186_memctrl_reconfig_mss_clients()
192 tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1); in tegra186_memctrl_reconfig_mss_clients()
356 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG1, val); in tegra186_memctrl_reconfig_mss_clients()
361 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG2, val); in tegra186_memctrl_reconfig_mss_clients()
365 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG3, val); in tegra186_memctrl_reconfig_mss_clients()
377 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG4, val); in tegra186_memctrl_reconfig_mss_clients()
381 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG5, val); in tegra186_memctrl_reconfig_mss_clients()
392 tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0); in tegra186_memctrl_reconfig_mss_clients()
398 tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1); in tegra186_memctrl_reconfig_mss_clients()
420 tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR, in tegra186_memctrl_set_overrides()
[all …]
/external/arm-trusted-firmware/plat/nvidia/tegra/include/drivers/
Dmemctrl_v1.h52 static inline void tegra_mc_write_32(uint32_t off, uint32_t val) in tegra_mc_write_32() function
Dmemctrl_v2.h67 static inline void tegra_mc_write_32(uint32_t off, uint32_t val) in tegra_mc_write_32() function
/external/arm-trusted-firmware/plat/nvidia/tegra/include/t186/
Dtegra_mc_def.h389 tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \