Searched refs:update_exec_mask (Results 1 – 22 of 22) sorted by relevance
| /external/mesa3d/src/gallium/drivers/r600/sb/ |
| D | sb_bc_builder.cpp | 435 .UPDATE_EXEC_MASK(bc.update_exec_mask) in build_alu()
450 .UPDATE_EXEC_MASK(bc.update_exec_mask) in build_alu()
464 .UPDATE_EXEC_MASK(bc.update_exec_mask) in build_alu()
479 .UPDATE_EXEC_MASK(bc.update_exec_mask) in build_alu()
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| D | sb_bc.h | 528 unsigned update_exec_mask:1; member
557 update_exec_mask = 0; in clear()
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| D | sb_bc_decoder.cpp | 376 bc.update_exec_mask = w1.get_UPDATE_EXEC_MASK(); in decode_alu()
395 bc.update_exec_mask = w1.get_UPDATE_EXEC_MASK(); in decode_alu()
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| D | sb_bc_dump.cpp | 380 s << (n.bc.update_exec_mask ? "M" : " "); in dump()
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| D | sb_bc_finalize.cpp | 341 n->bc.update_exec_mask = (n->dst[2] != NULL); in finalize_alu_group()
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| D | sb_bc_parser.cpp | 429 if (n->bc.update_exec_mask) in prepare_alu_group()
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| D | sb_expr.cpp | 1329 a->bc.update_exec_mask = 0; in convert_predset_to_set()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600InstrFormats.td | 125 bits<1> update_exec_mask;
132 let Word1{2} = update_exec_mask;
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| D | R600ExpandSpecialInstrs.cpp | 112 TII->setImmOperand(*PredSet, AMDGPU::OpName::update_exec_mask, 1); in runOnMachineFunction()
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| D | R600Instructions.td | 113 let update_exec_mask = 0;
137 (ins UEM:$update_exec_mask, UP:$update_pred, WRITE:$write,
144 "$clamp $last $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
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| D | R600InstrInfo.cpp | 1315 OPERAND_CASE(AMDGPU::OpName::update_exec_mask) in getSlotedOps()
1356 AMDGPU::OpName::update_exec_mask, in buildSlotOfVectorInstruction()
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| D | EvergreenInstructions.td | 417 let update_exec_mask = 0;
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | R600InstrFormats.td | 134 bits<1> update_exec_mask;
141 let Word1{2} = update_exec_mask;
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| D | R600ExpandSpecialInstrs.cpp | 127 TII->setImmOperand(*PredSet, R600::OpName::update_exec_mask, 1); in runOnMachineFunction()
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| D | R600InstrInfo.cpp | 1293 OPERAND_CASE(R600::OpName::update_exec_mask) in getSlotedOps()
1334 R600::OpName::update_exec_mask, in buildSlotOfVectorInstruction()
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| D | R600Instructions.td | 123 let update_exec_mask = 0;
147 (ins UEM:$update_exec_mask, UP:$update_pred, WRITE:$write,
154 "$clamp $last $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
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| D | EvergreenInstructions.td | 602 let update_exec_mask = 0;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600InstrFormats.td | 134 bits<1> update_exec_mask;
141 let Word1{2} = update_exec_mask;
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| D | R600ExpandSpecialInstrs.cpp | 127 TII->setImmOperand(*PredSet, R600::OpName::update_exec_mask, 1); in runOnMachineFunction()
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| D | R600InstrInfo.cpp | 1292 OPERAND_CASE(R600::OpName::update_exec_mask) in getSlotedOps()
1333 R600::OpName::update_exec_mask, in buildSlotOfVectorInstruction()
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| D | R600Instructions.td | 123 let update_exec_mask = 0;
147 (ins UEM:$update_exec_mask, UP:$update_pred, WRITE:$write,
154 "$clamp $last $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
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| D | EvergreenInstructions.td | 491 let update_exec_mask = 0;
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