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/external/llvm-project/llvm/test/CodeGen/ARM/
Dacle-intrinsics.ll50 define i32 @usat16(i32 %a) nounwind {
51 ; CHECK-LABEL: usat16
52 ; CHECK: usat16 r0, #0, r0
53 ; CHECK: usat16 r0, #15, r0
54 %tmp = call i32 @llvm.arm.usat16(i32 %a, i32 0)
55 %tmp2 = call i32 @llvm.arm.usat16(i32 %tmp, i32 15)
426 declare i32 @llvm.arm.usat16(i32, i32) nounwind
/external/llvm/test/MC/Disassembler/ARM/
Dthumb-tests.txt287 # CHECK: usat16 r4, #10, r1
Dthumb2.txt2532 # CHECK: usat16 r2, #2, r7
2533 # CHECK: usat16 r3, #15, r5
Dbasic-arm-instructions.txt2397 # CHECK: usat16 r2, #2, r7
2398 # CHECK: usat16 r3, #15, r5
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dthumb-tests.txt290 # CHECK: usat16 r4, #10, r1
Dbasic-arm-instructions.txt2397 # CHECK: usat16 r2, #2, r7
2398 # CHECK: usat16 r3, #15, r5
Dthumb2.txt2532 # CHECK: usat16 r2, #2, r7
2533 # CHECK: usat16 r3, #15, r5
/external/capstone/suite/MC/ARM/
Dbasic-thumb2-instructions.s.cs1143 0xa7,0xf3,0x02,0x02 = usat16 r2, #2, r7
1144 0xa5,0xf3,0x0f,0x03 = usat16 r3, #15, r5
Dbasic-arm-instructions.s.cs948 0x37,0x2f,0xe2,0xe6 = usat16 r2, #2, r7
949 0x35,0x3f,0xef,0xe6 = usat16 r3, #15, r5
/external/llvm-project/llvm/test/tools/llvm-mca/ARM/
Dcortex-a57-basic-instructions.s821 usat16 r2, #2, r7
822 usat16 r3, #15, r5
1691 # CHECK-NEXT: 1 2 1.00 usat16 r2, #2, r7
1692 # CHECK-NEXT: 1 2 1.00 usat16 r3, #15, r5
2568 # CHECK-NEXT: - - - - 1.00 - - - usat16 r2, #2, r7
2569 # CHECK-NEXT: - - - - 1.00 - - - usat16 r3, #15, r5
Dcortex-a57-thumb.s846 usat16 r2, #2, r7
847 usat16 r3, #15, r5
1753 # CHECK-NEXT: 1 2 1.00 usat16 r2, #2, r7
1754 # CHECK-NEXT: 1 2 1.00 usat16 r3, #15, r5
2667 # CHECK-NEXT: - - - - 1.00 - - - usat16 r2, #2, r7
2668 # CHECK-NEXT: - - - - 1.00 - - - usat16 r3, #15, r5
Dm7-int.s411 usat16 r0, #1, r1 label
839 # CHECK-NEXT: 1 3 1.00 usat16 r0, #1, r1
1279 …50 - - - - 1.00 1.00 - - - - - usat16 r0, #1, r1
Dm4-int.s424 usat16 r0, #1, r1 label
863 # CHECK-NEXT: 1 1 1.00 usat16 r0, #1, r1
1301 # CHECK-NEXT: 1.00 usat16 r0, #1, r1
/external/llvm-project/llvm/test/MC/ARM/
Dbasic-arm-instructions.s3434 usat16 r2, #2, r7
3435 usat16 r3, #15, r5
3437 @ CHECK: usat16 r2, #2, r7 @ encoding: [0x37,0x2f,0xe2,0xe6]
3438 @ CHECK: usat16 r3, #15, r5 @ encoding: [0x35,0x3f,0xef,0xe6]
Dbasic-thumb2-instructions.s3790 usat16 r2, #2, r7
3791 usat16 r3, #15, r5
3793 @ CHECK: usat16 r2, #2, r7 @ encoding: [0xa7,0xf3,0x02,0x02]
3794 @ CHECK: usat16 r3, #15, r5 @ encoding: [0xa5,0xf3,0x0f,0x03]
/external/llvm/test/MC/ARM/
Dbasic-arm-instructions.s3404 usat16 r2, #2, r7
3405 usat16 r3, #15, r5
3407 @ CHECK: usat16 r2, #2, r7 @ encoding: [0x37,0x2f,0xe2,0xe6]
3408 @ CHECK: usat16 r3, #15, r5 @ encoding: [0x35,0x3f,0xef,0xe6]
Dbasic-thumb2-instructions.s3531 usat16 r2, #2, r7
3532 usat16 r3, #15, r5
3534 @ CHECK: usat16 r2, #2, r7 @ encoding: [0xa7,0xf3,0x02,0x02]
3535 @ CHECK: usat16 r3, #15, r5 @ encoding: [0xa5,0xf3,0x0f,0x03]
/external/vixl/src/aarch32/
Dassembler-aarch32.h3726 void usat16(Condition cond, Register rd, uint32_t imm, Register rn);
3727 void usat16(Register rd, uint32_t imm, Register rn) { in usat16() function
3728 usat16(al, rd, imm, rn); in usat16()
Ddisasm-aarch32.h1419 void usat16(Condition cond, Register rd, uint32_t imm, Register rn);
/external/capstone/arch/AArch64/
DARMMappingInsnOp.inc1204 { /* ARM_USAT16, ARM_INS_USAT16: usat16${p} $rd, $sat_imm, $rn */
6385 { /* ARM_t2USAT16, ARM_INS_USAT16: usat16${p} $rd, $sat_imm, $rn */
/external/capstone/arch/ARM/
DARMMappingInsnOp.inc1204 { /* ARM_USAT16, ARM_INS_USAT16: usat16${p} $rd, $sat_imm, $rn */
6385 { /* ARM_t2USAT16, ARM_INS_USAT16: usat16${p} $rd, $sat_imm, $rn */
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td2277 "usat16", "\t$Rd, $sat_imm, $Rn", []>,
DARMInstrInfo.td3698 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrThumb2.td2571 "usat16", "\t$Rd, $sat_imm, $Rn">,
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrThumb2.td2619 "usat16", "\t$Rd, $sat_imm, $Rn">,

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