| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | reserve-vgpr-for-sgpr-spill.ll | 34 ,~{v100},~{v101},~{v102},~{v103},~{v104},~{v105},~{v106},~{v107},~{v108},~{v109}
79 ,~{v100},~{v101},~{v102},~{v103},~{v104},~{v105},~{v106},~{v107},~{v108},~{v109}
121 ,~{v100},~{v101},~{v102},~{v103},~{v104},~{v105},~{v106},~{v107},~{v108},~{v109}
170 ,~{v100},~{v101},~{v102},~{v103},~{v104},~{v105},~{v106},~{v107},~{v108},~{v109}
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| /external/llvm-project/llvm/test/CodeGen/Hexagon/ |
| D | bug14859-split-const-block-addr.ll | 241 %v100 = phi i8* [ %v101, %b31 ], [ %v83, %b24 ]
242 %v101 = getelementptr inbounds i8, i8* %v100, i32 -1
243 %v102 = load i8, i8* %v101, align 1, !tbaa !4
249 %v105 = phi i8* [ %v101, %b32 ], [ %v86, %b30 ]
250 %v106 = phi i8* [ %v101, %b32 ], [ %v6, %b30 ]
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| D | swp-disable-Os.ll | 122 %v101 = or i32 %v100, %v99
123 ret i32 %v101
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| D | swp-phi.ll | 115 %v101 = add nsw i32 %v67, 16
116 %v102 = getelementptr inbounds [400 x float], [400 x float]* %v0, i32 0, i32 %v101
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| D | aggr-licm.ll | 121 %v101 = lshr i64 %v3, 16
123 %v103 = and i64 %v101, 1
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| D | fltnvjump.ll | 166 %v101 = load i16*, i16** %v18, align 4, !tbaa !0
168 call void @f6(i16* %v100, i16 signext %v94, i16* %v101, i16 signext %v102)
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| D | swp-epilog-phi5.ll | 174 %v101 = icmp slt i32 %v98, %v100
175 br i1 %v101, label %b2, label %b9
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| D | swp-conv3x3-nested.ll | 151 %v101 = icmp sgt i32 %v47, 64
152 br i1 %v101, label %b4, label %b5
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| D | registerscavenger-fail1.ll | 197 %v101 = fptosi double %v100 to i32
209 %v107 = phi i32 [ %v101, %b25 ], [ %v91, %b24 ]
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| D | late_instr.ll | 128 %v101 = tail call <16 x i32> @llvm.hexagon.V6.vminub(<16 x i32> %v97, <16 x i32> %v99)
130 %v103 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v101, <16 x i32> %v96)
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| D | reg-scavengebug-5.ll | 63 %v45 = phi <16 x i32> [ %v101, %b2 ], [ %v8, %b1 ]
123 %v101 = load <16 x i32>, <16 x i32>* %v82, align 64
143 %v119 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v113, <16 x i32> %v101, i32 1)
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| D | v60-vecpred-spill.ll | 128 %v101 = icmp slt i32 %v100, %v4
129 br i1 %v101, label %b2, label %b5
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| D | SUnit-boundary-prob.ll | 137 %v101 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v97) #2
138 …%v102 = tail call <16 x i32> @llvm.hexagon.V6.vaslw.acc(<16 x i32> %v100, <16 x i32> %v101, i32 16…
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| D | cext-ice.ll | 210 %v101 = mul nsw i32 %v100, 4
211 %v102 = add nsw i32 %v101, 268435456
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| D | swp-sigma.ll | 154 %v101 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v99) #2
156 %v103 = tail call <16 x i32> @llvm.hexagon.V6.vmpyhvsrs(<16 x i32> %v101, <16 x i32> %v102) #2
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| D | large-number-of-preds.ll | 165 %v101 = getelementptr inbounds [8 x float], [8 x float]* %v1, i32 0, i32 2
166 store float %v86, float* %v101, align 8, !tbaa !0
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| D | reg-scavengebug-4.ll | 124 %v101 = tail call <16 x i32> @llvm.hexagon.V6.vshuffeb(<16 x i32> %v100, <16 x i32> undef)
126 store <16 x i32> %v101, <16 x i32>* %v2, align 64
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| D | reg-scavengebug.ll | 135 %v101 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v100, <16 x i32> %v82, i32 4)
137 %v103 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v101, <16 x i32> %v102)
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| D | regscavenger_fail_hwloop.ll | 126 %v101 = add nsw i32 %v88, %v80
127 %v102 = mul i32 %v101, -5
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| D | lsr-post-inc-cross-use-offsets.ll | 164 %v101 = getelementptr inbounds i8, i8* %v1, i32 %v100
165 %v102 = bitcast i8* %v101 to <32 x i32>*
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| D | expand-vstorerw-undef2.ll | 160 …%v101 = tail call <32 x i32> @llvm.hexagon.V6.valignb.128B(<32 x i32> undef, <32 x i32> %v36, i32 …
161 %v102 = tail call <32 x i32> @llvm.hexagon.V6.vsubhsat.128B(<32 x i32> %v100, <32 x i32> %v101) #2
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| D | swp-epilog-phi7.ll | 128 %v101 = phi <16 x i32> [ %v12, %b1 ], [ %v102, %b2 ]
141 %v114 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v102, <16 x i32> %v101, i32 1)
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| D | reg-scav-imp-use-dbl-vec.ll | 194 %v101 = tail call <32 x i32> @llvm.hexagon.V6.vshufeh.128B(<32 x i32> undef, <32 x i32> %v100) #3
198 store <32 x i32> %v101, <32 x i32>* %v104, align 128, !tbaa !6
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| /external/llvm-project/llvm/test/Transforms/LoopVectorize/Hexagon/ |
| D | minimum-vf.ll | 129 %v101 = add i32 145, %v21
130 %v102 = getelementptr inbounds i8, i8* %v14, i32 %v101
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| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| D | lp_bld_arit.h | 165 LLVMValueRef v101,
|