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/external/llvm-project/llvm/test/Analysis/CostModel/X86/
Dreduce-fmax.ll52 …d cost of 11 for instruction: %V32 = call float @llvm.vector.reduce.fmax.v32f32(<32 x float> undef)
61 …ed cost of 9 for instruction: %V32 = call float @llvm.vector.reduce.fmax.v32f32(<32 x float> undef)
70 …ed cost of 9 for instruction: %V32 = call float @llvm.vector.reduce.fmax.v32f32(<32 x float> undef)
78 %V32 = call float @llvm.vector.reduce.fmax.v32f32(<32 x float> undef)
93 declare float @llvm.vector.reduce.fmax.v32f32(<32 x float>)
Dreduce-fmin.ll52 …d cost of 11 for instruction: %V32 = call float @llvm.vector.reduce.fmin.v32f32(<32 x float> undef)
61 …ed cost of 9 for instruction: %V32 = call float @llvm.vector.reduce.fmin.v32f32(<32 x float> undef)
70 …ed cost of 9 for instruction: %V32 = call float @llvm.vector.reduce.fmin.v32f32(<32 x float> undef)
78 %V32 = call float @llvm.vector.reduce.fmin.v32f32(<32 x float> undef)
93 declare float @llvm.vector.reduce.fmin.v32f32(<32 x float>)
Dreduce-fadd.ll84 …d cost of 18 for instruction: %V32 = call float @llvm.vector.reduce.fadd.v32f32(float %arg, <32 x …
93 …d cost of 18 for instruction: %V32 = call float @llvm.vector.reduce.fadd.v32f32(float %arg, <32 x …
102 …d cost of 18 for instruction: %V32 = call float @llvm.vector.reduce.fadd.v32f32(float %arg, <32 x …
111 …d cost of 11 for instruction: %V32 = call float @llvm.vector.reduce.fadd.v32f32(float %arg, <32 x …
120 …d cost of 10 for instruction: %V32 = call float @llvm.vector.reduce.fadd.v32f32(float %arg, <32 x …
129 …ed cost of 7 for instruction: %V32 = call float @llvm.vector.reduce.fadd.v32f32(float %arg, <32 x …
138 …ed cost of 9 for instruction: %V32 = call float @llvm.vector.reduce.fadd.v32f32(float %arg, <32 x …
146 %V32 = call float @llvm.vector.reduce.fadd.v32f32(float %arg, <32 x float> undef)
161 declare float @llvm.vector.reduce.fadd.v32f32(float, <32 x float>)
Dreduce-fmul.ll84 …d cost of 20 for instruction: %V32 = call float @llvm.vector.reduce.fmul.v32f32(float %arg, <32 x …
93 …d cost of 20 for instruction: %V32 = call float @llvm.vector.reduce.fmul.v32f32(float %arg, <32 x …
102 …d cost of 20 for instruction: %V32 = call float @llvm.vector.reduce.fmul.v32f32(float %arg, <32 x …
111 …d cost of 11 for instruction: %V32 = call float @llvm.vector.reduce.fmul.v32f32(float %arg, <32 x …
120 …d cost of 12 for instruction: %V32 = call float @llvm.vector.reduce.fmul.v32f32(float %arg, <32 x …
129 …ed cost of 9 for instruction: %V32 = call float @llvm.vector.reduce.fmul.v32f32(float %arg, <32 x …
138 …ed cost of 9 for instruction: %V32 = call float @llvm.vector.reduce.fmul.v32f32(float %arg, <32 x …
146 %V32 = call float @llvm.vector.reduce.fmul.v32f32(float %arg, <32 x float> undef)
161 declare float @llvm.vector.reduce.fmul.v32f32(float, <32 x float>)
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h132 v32f32 = 77, // 32 x f32 enumerator
524 case v32f32: in getVectorElementType()
579 case v32f32: in getVectorNumElements()
808 case v32f32: return TypeSize::Fixed(1024); in getSizeInBits()
1000 if (NumElements == 32) return MVT::v32f32; in getVectorVT()
/external/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h146 v32f32 = 91, // 32 x f32 enumerator
411 SimpleTy == MVT::v32f32 || SimpleTy == MVT::v16f64 || in is1024BitVector()
612 case v32f32: in getVectorElementType()
685 case v32f32: in getVectorNumElements()
949 case v32f32: in getSizeInBits()
1202 if (NumElements == 32) return MVT::v32f32; in getVectorVT()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td586 def SGPR_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32,
591 def SReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32,
647 def VReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32,
678 def AReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32,
DSIInstrInfo.td2307 def VOP_V32F32_F32_F32_V32F32 : VOPProfile <[v32f32, f32, f32, v32f32]>;
2310 def VOP_V32F32_V4F16_V4F16_V32F32 : VOPProfile <[v32f32, v4f16, v4f16, v32f32]>;
2313 def VOP_V32F32_V2I16_V2I16_V32F32 : VOPProfile <[v32f32, v2i16, v2i16, v32f32]>;
DSIInstructions.td959 f32, v32f32, Index, !cast<SubRegIndex>(sub#Index)
963 f32, v32f32, Index, !cast<SubRegIndex>(sub#Index)
1058 def : BitConvert <v32i32, v32f32, VReg_1024>;
1059 def : BitConvert <v32f32, v32i32, VReg_1024>;
DAMDGPUISelLowering.cpp91 setOperationAction(ISD::LOAD, MVT::v32f32, Promote); in AMDGPUTargetLowering()
92 AddPromotedToType(ISD::LOAD, MVT::v32f32, MVT::v32i32); in AMDGPUTargetLowering()
158 setLoadExtAction(ISD::EXTLOAD, MVT::v32f32, MVT::v32f16, Expand); in AMDGPUTargetLowering()
191 setOperationAction(ISD::STORE, MVT::v32f32, Promote); in AMDGPUTargetLowering()
192 AddPromotedToType(ISD::STORE, MVT::v32f32, MVT::v32i32); in AMDGPUTargetLowering()
222 setTruncStoreAction(MVT::v32f32, MVT::v32f16, Expand); in AMDGPUTargetLowering()
298 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32f32, Custom); in AMDGPUTargetLowering()
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-fixed-length-fp-rounding.ll171 %res = call <32 x float> @llvm.ceil.v32f32(<32 x float> %op)
418 %res = call <32 x float> @llvm.floor.v32f32(<32 x float> %op)
665 %res = call <32 x float> @llvm.nearbyint.v32f32(<32 x float> %op)
912 %res = call <32 x float> @llvm.rint.v32f32(<32 x float> %op)
1159 %res = call <32 x float> @llvm.round.v32f32(<32 x float> %op)
1406 %res = call <32 x float> @llvm.trunc.v32f32(<32 x float> %op)
1517 declare <32 x float> @llvm.ceil.v32f32(<32 x float>)
1536 declare <32 x float> @llvm.floor.v32f32(<32 x float>)
1555 declare <32 x float> @llvm.nearbyint.v32f32(<32 x float>)
1574 declare <32 x float> @llvm.rint.v32f32(<32 x float>)
[all …]
Dsve-fixed-length-fp-reduce.ll158 %res = call float @llvm.vector.reduce.fadd.v32f32(float %start, <32 x float> %op)
393 %res = call fast float @llvm.vector.reduce.fadd.v32f32(float %start, <32 x float> %op)
617 %res = call float @llvm.vector.reduce.fmax.v32f32(<32 x float> %op)
834 %res = call float @llvm.vector.reduce.fmin.v32f32(<32 x float> %op)
933 declare float @llvm.vector.reduce.fadd.v32f32(float, <32 x float>)
954 declare float @llvm.vector.reduce.fmax.v32f32(<32 x float>)
975 declare float @llvm.vector.reduce.fmin.v32f32(<32 x float>)
Dsve-fixed-length-fp-minmax.ll191 %res = call <32 x float> @llvm.maxnum.v32f32(<32 x float> %op1, <32 x float> %op2)
471 %res = call <32 x float> @llvm.minnum.v32f32(<32 x float> %op1, <32 x float> %op2)
595 declare <32 x float> @llvm.minnum.v32f32(<32 x float>, <32 x float>)
614 declare <32 x float> @llvm.maxnum.v32f32(<32 x float>, <32 x float>)
Dsve-fixed-length-fp-arith.ll701 %res = call <32 x float> @llvm.fma.v32f32(<32 x float> %op1, <32 x float> %op2, <32 x float> %op3)
1387 %res = call <32 x float> @llvm.sqrt.v32f32(<32 x float> %op)
1725 declare <32 x float> @llvm.fma.v32f32(<32 x float>, <32 x float>, <32 x float>)
1744 declare <32 x float> @llvm.sqrt.v32f32(<32 x float>)
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td777 def SGPR_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32, v16i64, v16f64], 32,
782 def SReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32, v16i64, v16f64], 32,
807 def VReg_1024 : VRegClass<32, [v32i32, v32f32, v16i64, v16f64], (add VGPR_1024)>;
823 def AReg_1024 : ARegClass<32, [v32i32, v32f32, v16i64, v16f64], (add AGPR_1024)>;
DSIInstructions.td1101 f32, v32f32, Index, !cast<SubRegIndex>(sub#Index)
1105 f32, v32f32, Index, !cast<SubRegIndex>(sub#Index)
1223 def : BitConvert <v32i32, v32f32, VReg_1024>;
1224 def : BitConvert <v32f32, v32i32, VReg_1024>;
1229 def : BitConvert <v16f64, v32f32, VReg_1024>;
1230 def : BitConvert <v32f32, v16f64, VReg_1024>;
1231 def : BitConvert <v16i64, v32f32, VReg_1024>;
1234 def : BitConvert <v32f32, v16i64, VReg_1024>;
1701 defm : SI_INDIRECT_Pattern <v32f32, f32, "V32">;
DSIInstrInfo.td2292 def VOP_V32F32_F32_F32_V32F32 : VOPProfile <[v32f32, f32, f32, v32f32]>;
2295 def VOP_V32F32_V4F16_V4F16_V32F32 : VOPProfile <[v32f32, v4f16, v4f16, v32f32]>;
2298 def VOP_V32F32_V2I16_V2I16_V32F32 : VOPProfile <[v32f32, v2i16, v2i16, v32f32]>;
DAMDGPUISelLowering.cpp95 setOperationAction(ISD::LOAD, MVT::v32f32, Promote); in AMDGPUTargetLowering()
96 AddPromotedToType(ISD::LOAD, MVT::v32f32, MVT::v32i32); in AMDGPUTargetLowering()
180 setLoadExtAction(ISD::EXTLOAD, MVT::v32f32, MVT::v32f16, Expand); in AMDGPUTargetLowering()
215 setOperationAction(ISD::STORE, MVT::v32f32, Promote); in AMDGPUTargetLowering()
216 AddPromotedToType(ISD::STORE, MVT::v32f32, MVT::v32i32); in AMDGPUTargetLowering()
264 setTruncStoreAction(MVT::v32f32, MVT::v32f16, Expand); in AMDGPUTargetLowering()
350 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32f32, Custom); in AMDGPUTargetLowering()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DValueTypes.cpp222 case MVT::v32f32: return VectorType::get(Type::getFloatTy(Context), 32); in getTypeForEVT()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.td104 def v32f32 : ValueType<1024, 77>; // 32 x f32 vector value
/external/llvm-project/llvm/include/llvm/CodeGen/
DValueTypes.td119 def v32f32 : ValueType<1024, 91>; // 32 x f32 vector value
/external/llvm-project/llvm/lib/CodeGen/
DValueTypes.cpp350 case MVT::v32f32: in getTypeForEVT()
/external/llvm-project/llvm/utils/TableGen/
DCodeGenTarget.cpp157 case MVT::v32f32: return "MVT::v32f32"; in getEnumName()
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dspill-vgpr-to-agpr.ll234 ; FIXME: adding an AReg_1024 register class for v32f32 and v32i32
/external/llvm-project/llvm/test/Transforms/SLPVectorizer/X86/
Dhorizontal-list.ll393 ; CHECK-NEXT: [[TMP4:%.*]] = call fast float @llvm.vector.reduce.fadd.v32f32(float -0.000000e+00…
451 ; THRESHOLD-NEXT: [[TMP4:%.*]] = call fast float @llvm.vector.reduce.fadd.v32f32(float -0.000000…
640 ; CHECK-NEXT: [[TMP2:%.*]] = call fast float @llvm.vector.reduce.fadd.v32f32(float -0.000000e+00…
681 ; THRESHOLD-NEXT: [[TMP2:%.*]] = call fast float @llvm.vector.reduce.fadd.v32f32(float -0.000000…

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