Home
last modified time | relevance | path

Searched refs:v8i64 (Results 1 – 25 of 185) sorted by relevance

12345678

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp306 { ISD::SRA, MVT::v8i64, 1 }, in getArithmeticInstrCost()
489 { ISD::MUL, MVT::v8i64, 1 } in getArithmeticInstrCost()
529 { ISD::SHL, MVT::v8i64, 1 }, in getArithmeticInstrCost()
530 { ISD::SRL, MVT::v8i64, 1 }, in getArithmeticInstrCost()
534 { ISD::SRA, MVT::v8i64, 1 }, in getArithmeticInstrCost()
541 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add in getArithmeticInstrCost()
1035 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq in getShuffleCost()
1040 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq in getShuffleCost()
1049 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq in getShuffleCost()
1059 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q in getShuffleCost()
[all …]
DX86InstrVecCompiler.td84 defm : subvector_subreg_lowering<VR128, v2i64, VR512, v8i64, sub_xmm>;
95 defm : subvector_subreg_lowering<VR256, v4i64, VR512, v8i64, sub_ymm>;
133 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v8i64, v2i64, v16i32, sub_xmm>;
140 defm : subvec_zero_lowering<"DQA64Z256", VR256X, v8i64, v4i64, v16i32, sub_ymm>;
149 defm : subvec_zero_lowering<"DQA", VR128, v8i64, v2i64, v16i32, sub_xmm>;
156 defm : subvec_zero_lowering<"DQAY", VR256, v8i64, v4i64, v16i32, sub_ymm>;
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h98 v8i64 = 48, // 8 x i64 enumerator
267 SimpleTy == MVT::v8i64); in is512BitVector()
352 case v8i64: in getVectorElementType()
399 case v8i64: in getVectorNumElements()
500 case v8i64: in getSizeInBits()
636 if (NumElements == 8) return MVT::v8i64; in getVectorVT()
/external/llvm-project/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp319 { ISD::SRA, MVT::v8i64, 1 }, in getArithmeticInstrCost()
554 { ISD::MUL, MVT::v8i64, 1 } in getArithmeticInstrCost()
582 { ISD::SHL, MVT::v8i64, 1 }, in getArithmeticInstrCost()
583 { ISD::SRL, MVT::v8i64, 1 }, in getArithmeticInstrCost()
587 { ISD::SRA, MVT::v8i64, 1 }, in getArithmeticInstrCost()
595 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add in getArithmeticInstrCost()
1144 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq in getShuffleCost()
1151 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq in getShuffleCost()
1160 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq in getShuffleCost()
1170 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q in getShuffleCost()
[all …]
DX86InstrVecCompiler.td84 defm : subvector_subreg_lowering<VR128, v2i64, VR512, v8i64, sub_xmm>;
95 defm : subvector_subreg_lowering<VR256, v4i64, VR512, v8i64, sub_ymm>;
133 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v8i64, v2i64, v16i32, sub_xmm>;
140 defm : subvec_zero_lowering<"DQA64Z256", VR256X, v8i64, v4i64, v16i32, sub_ymm>;
149 defm : subvec_zero_lowering<"DQA", VR128, v8i64, v2i64, v16i32, sub_xmm>;
156 defm : subvec_zero_lowering<"DQAY", VR256, v8i64, v4i64, v16i32, sub_ymm>;
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp138 { ISD::SHL, MVT::v8i64, 1 }, in getArithmeticInstrCost()
139 { ISD::SRL, MVT::v8i64, 1 }, in getArithmeticInstrCost()
140 { ISD::SRA, MVT::v8i64, 1 }, in getArithmeticInstrCost()
539 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, in getCastInstrCost()
540 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, in getCastInstrCost()
544 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, in getCastInstrCost()
547 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, in getCastInstrCost()
560 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 1 }, in getCastInstrCost()
561 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, in getCastInstrCost()
570 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, in getCastInstrCost()
[all …]
DX86CallingConv.td68 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
122 CCIfType<[v16f32, v8f64, v16i32, v8i64],
149 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
346 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
366 CCIfType<[v16i32, v8i64, v16f32, v8f64],
406 CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
449 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
524 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
541 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
560 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
[all …]
/external/llvm-project/llvm/test/CodeGen/X86/
Davx512vpopcntdq-intrinsics.ll62 %1 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %a)
81 %1 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %a)
88 declare <8 x i64> @llvm.ctpop.v8i64(<8 x i64>)
Davx512cd-intrinsics.ll116 %1 = call <8 x i64> @llvm.ctlz.v8i64(<8 x i64> %a, i1 false)
119 declare <8 x i64> @llvm.ctlz.v8i64(<8 x i64>, i1) #0
156 %1 = call <8 x i64> @llvm.ctlz.v8i64(<8 x i64> %a, i1 false)
Davx512vbmi2-intrinsics-fast-isel.ll320 …%0 = tail call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %__A, <8 x i64> %__B, <8 x i64> <i64 47, i64 4…
326 declare <8 x i64> @llvm.fshl.v8i64(<8 x i64>, <8 x i64>, <8 x i64>)
342 …%0 = tail call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %__A, <8 x i64> %__B, <8 x i64> <i64 63, i64 6…
354 …%0 = tail call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %__A, <8 x i64> %__B, <8 x i64> <i64 31, i64 3…
492 …%0 = tail call <8 x i64> @llvm.fshr.v8i64(<8 x i64> %__B, <8 x i64> %__A, <8 x i64> <i64 47, i64 4…
498 declare <8 x i64> @llvm.fshr.v8i64(<8 x i64>, <8 x i64>, <8 x i64>)
514 …%0 = tail call <8 x i64> @llvm.fshr.v8i64(<8 x i64> %__B, <8 x i64> %__A, <8 x i64> <i64 63, i64 6…
526 …%0 = tail call <8 x i64> @llvm.fshr.v8i64(<8 x i64> %__B, <8 x i64> %__A, <8 x i64> <i64 31, i64 3…
664 %0 = tail call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %__S, <8 x i64> %__A, <8 x i64> %__B)
684 %0 = tail call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %__S, <8 x i64> %__A, <8 x i64> %__B)
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dregbankselect-load.mir27 %global.not.uniform.v8i64 = getelementptr <8 x i64>, <8 x i64> addrspace(1)* %in, i32 %tmp0
28 %tmp2 = load <8 x i64>, <8 x i64> addrspace(1)* %global.not.uniform.v8i64
70 %constant.not.uniform.v8i64 = getelementptr <8 x i64>, <8 x i64> addrspace(4)* %in, i32 %tmp0
71 %tmp2 = load <8 x i64>, <8 x i64> addrspace(4)* %constant.not.uniform.v8i64
181 …r(<2 x s64>) = G_LOAD [[PTR]](p1) :: (load 16 from %ir.global.not.uniform.v8i64, align 64, addrspa…
184 …<2 x s64>) = G_LOAD [[GEP16]](p1) :: (load 16 from %ir.global.not.uniform.v8i64 + 16, align 64, ad…
187 …<2 x s64>) = G_LOAD [[GEP32]](p1) :: (load 16 from %ir.global.not.uniform.v8i64 + 32, align 64, ad…
190 …<2 x s64>) = G_LOAD [[GEP48]](p1) :: (load 16 from %ir.global.not.uniform.v8i64 + 48, align 64, ad…
193 %1:_(<8 x s64>) = G_LOAD %0 :: (load 64 from %ir.global.not.uniform.v8i64)
364 …2 x s64>) = G_LOAD [[COPY]](p4) :: (load 16 from %ir.constant.not.uniform.v8i64, align 64, addrspa…
[all …]
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dknown-non-zero.ll8 declare <8 x i64> @llvm.cttz.v8i64(<8 x i64>, i1)
72 ; CHECK-NEXT: [[CTZ:%.*]] = call <8 x i64> @llvm.cttz.v8i64(<8 x i64> [[X]], i1 false)
87 %ctz = call <8 x i64> @llvm.cttz.v8i64(<8 x i64> %x, i1 false)
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h110 v8i64 = 60, // 8 x i64 enumerator
370 SimpleTy == MVT::v16i32 || SimpleTy == MVT::v8i64); in is512BitVector()
498 case v8i64: in getVectorElementType()
602 case v8i64: in getVectorNumElements()
794 case v8i64: in getSizeInBits()
977 if (NumElements == 8) return MVT::v8i64; in getVectorVT()
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp205 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
206 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
207 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
208 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
450 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 8 * AmortizationCost }, in getCmpSelInstrCost()
/external/llvm-project/llvm/test/Analysis/CostModel/ARM/
Dreduce-add.ll12 …estimated cost of 44 for instruction: %V8 = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> undef)
20 …estimated cost of 55 for instruction: %V8 = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> undef)
28 …estimated cost of 44 for instruction: %V8 = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> undef)
36 …estimated cost of 54 for instruction: %V8 = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> undef)
43 %V8 = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> undef)
102 declare i64 @llvm.vector.reduce.add.v8i64(<8 x i64>)
Darith-usat.ll12 declare <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64>, <8 x i64>)
34 …imated cost of 72 for instruction: %V8I64 = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> undef, <…
53 …imated cost of 58 for instruction: %V8I64 = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> undef, <…
72 …mated cost of 448 for instruction: %V8I64 = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> undef, <…
91 …imated cost of 18 for instruction: %V8I64 = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> undef, <…
110 …imated cost of 52 for instruction: %V8I64 = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> undef, <…
129 …mated cost of 146 for instruction: %V8I64 = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> undef, <…
147 %V8I64 = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
170 declare <8 x i64> @llvm.usub.sat.v8i64(<8 x i64>, <8 x i64>)
192 …imated cost of 72 for instruction: %V8I64 = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> undef, <…
[all …]
Darith-ssat.ll12 declare <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64>, <8 x i64>)
34 …mated cost of 216 for instruction: %V8I64 = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> undef, <…
53 …mated cost of 123 for instruction: %V8I64 = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> undef, <…
72 …ated cost of 1046 for instruction: %V8I64 = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> undef, <…
91 …imated cost of 32 for instruction: %V8I64 = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> undef, <…
110 …mated cost of 108 for instruction: %V8I64 = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> undef, <…
129 …mated cost of 153 for instruction: %V8I64 = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> undef, <…
147 %V8I64 = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
170 declare <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64>, <8 x i64>)
192 …mated cost of 216 for instruction: %V8I64 = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> undef, <…
[all …]
Darith-overflow.ll12 declare {<8 x i64>, <8 x i1>} @llvm.sadd.with.overflow.v8i64(<8 x i64>, <8 x i64>)
34 …struction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.sadd.with.overflow.v8i64(<8 x i64> undef, <…
53 …struction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.sadd.with.overflow.v8i64(<8 x i64> undef, <…
72 …struction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.sadd.with.overflow.v8i64(<8 x i64> undef, <…
91 …struction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.sadd.with.overflow.v8i64(<8 x i64> undef, <…
110 …struction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.sadd.with.overflow.v8i64(<8 x i64> undef, <…
129 …struction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.sadd.with.overflow.v8i64(<8 x i64> undef, <…
147 …%V8I64 = call {<8 x i64>, <8 x i1>} @llvm.sadd.with.overflow.v8i64(<8 x i64> undef, <8 x i64> unde…
170 declare {<8 x i64>, <8 x i1>} @llvm.uadd.with.overflow.v8i64(<8 x i64>, <8 x i64>)
192 …struction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.uadd.with.overflow.v8i64(<8 x i64> undef, <…
[all …]
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp117 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
118 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
119 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
120 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
302 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 }, in getCmpSelInstrCost()
/external/llvm-project/llvm/test/Analysis/CostModel/X86/
Darith-uminmax.ll14 declare <8 x i64> @llvm.umax.v8i64(<8 x i64>, <8 x i64>)
36 … estimated cost of 44 for instruction: %V8I64 = call <8 x i64> @llvm.umax.v8i64(<8 x i64> undef, <…
55 … estimated cost of 44 for instruction: %V8I64 = call <8 x i64> @llvm.umax.v8i64(<8 x i64> undef, <…
74 …n estimated cost of 8 for instruction: %V8I64 = call <8 x i64> @llvm.umax.v8i64(<8 x i64> undef, <…
93 … estimated cost of 10 for instruction: %V8I64 = call <8 x i64> @llvm.umax.v8i64(<8 x i64> undef, <…
112 …n estimated cost of 4 for instruction: %V8I64 = call <8 x i64> @llvm.umax.v8i64(<8 x i64> undef, <…
131 …n estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.umax.v8i64(<8 x i64> undef, <…
150 …n estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.umax.v8i64(<8 x i64> undef, <…
169 …n estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.umax.v8i64(<8 x i64> undef, <…
187 %V8I64 = call <8 x i64> @llvm.umax.v8i64(<8 x i64> undef, <8 x i64> undef)
[all …]
Darith-sminmax.ll14 declare <8 x i64> @llvm.smax.v8i64(<8 x i64>, <8 x i64>)
36 … estimated cost of 44 for instruction: %V8I64 = call <8 x i64> @llvm.smax.v8i64(<8 x i64> undef, <…
55 … estimated cost of 44 for instruction: %V8I64 = call <8 x i64> @llvm.smax.v8i64(<8 x i64> undef, <…
74 …n estimated cost of 8 for instruction: %V8I64 = call <8 x i64> @llvm.smax.v8i64(<8 x i64> undef, <…
93 … estimated cost of 10 for instruction: %V8I64 = call <8 x i64> @llvm.smax.v8i64(<8 x i64> undef, <…
112 …n estimated cost of 4 for instruction: %V8I64 = call <8 x i64> @llvm.smax.v8i64(<8 x i64> undef, <…
131 …n estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.smax.v8i64(<8 x i64> undef, <…
150 …n estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.smax.v8i64(<8 x i64> undef, <…
169 …n estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.smax.v8i64(<8 x i64> undef, <…
187 %V8I64 = call <8 x i64> @llvm.smax.v8i64(<8 x i64> undef, <8 x i64> undef)
[all …]
Darith-usat.ll21 declare <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64>, <8 x i64>)
43 …imated cost of 48 for instruction: %V8I64 = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> undef, <…
62 …imated cost of 12 for instruction: %V8I64 = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> undef, <…
81 …imated cost of 18 for instruction: %V8I64 = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> undef, <…
100 …timated cost of 6 for instruction: %V8I64 = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> undef, <…
119 …timated cost of 3 for instruction: %V8I64 = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> undef, <…
138 …timated cost of 3 for instruction: %V8I64 = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> undef, <…
157 …timated cost of 3 for instruction: %V8I64 = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> undef, <…
176 …imated cost of 28 for instruction: %V8I64 = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> undef, <…
195 …imated cost of 12 for instruction: %V8I64 = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> undef, <…
[all …]
Darith-ssat.ll20 declare <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64>, <8 x i64>)
42 …mated cost of 163 for instruction: %V8I64 = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> undef, <…
61 …imated cost of 31 for instruction: %V8I64 = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> undef, <…
80 …imated cost of 47 for instruction: %V8I64 = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> undef, <…
99 …imated cost of 17 for instruction: %V8I64 = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> undef, <…
118 …imated cost of 40 for instruction: %V8I64 = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> undef, <…
137 …imated cost of 40 for instruction: %V8I64 = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> undef, <…
156 …imated cost of 40 for instruction: %V8I64 = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> undef, <…
175 …imated cost of 59 for instruction: %V8I64 = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> undef, <…
194 …imated cost of 31 for instruction: %V8I64 = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> undef, <…
[all …]
Darith-fix.ll17 declare <8 x i64> @llvm.smul.fix.v8i64(<8 x i64>, <8 x i64>, i32)
39 …imated cost of 76 for instruction: %V8I64 = call <8 x i64> @llvm.smul.fix.v8i64(<8 x i64> undef, <…
58 …imated cost of 76 for instruction: %V8I64 = call <8 x i64> @llvm.smul.fix.v8i64(<8 x i64> undef, <…
77 …imated cost of 90 for instruction: %V8I64 = call <8 x i64> @llvm.smul.fix.v8i64(<8 x i64> undef, <…
96 …imated cost of 78 for instruction: %V8I64 = call <8 x i64> @llvm.smul.fix.v8i64(<8 x i64> undef, <…
115 …imated cost of 79 for instruction: %V8I64 = call <8 x i64> @llvm.smul.fix.v8i64(<8 x i64> undef, <…
134 …imated cost of 79 for instruction: %V8I64 = call <8 x i64> @llvm.smul.fix.v8i64(<8 x i64> undef, <…
153 …imated cost of 79 for instruction: %V8I64 = call <8 x i64> @llvm.smul.fix.v8i64(<8 x i64> undef, <…
172 …imated cost of 76 for instruction: %V8I64 = call <8 x i64> @llvm.smul.fix.v8i64(<8 x i64> undef, <…
191 …imated cost of 76 for instruction: %V8I64 = call <8 x i64> @llvm.smul.fix.v8i64(<8 x i64> undef, <…
[all …]
/external/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h111 v8i64 = 61, // 8 x i64 enumerator
403 SimpleTy == MVT::v8i64); in is512BitVector()
567 case v8i64: in getVectorElementType()
713 case v8i64: in getVectorNumElements()
930 case v8i64: in getSizeInBits()
1164 if (NumElements == 8) return MVT::v8i64; in getVectorVT()

12345678