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Searched refs:v_lshl_b64 (Results 1 – 25 of 47) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dshift-i64-opts.ll235 ; GCN: v_lshl_b64 v{{\[}}[[RESLO:[0-9]+]]:[[RESHI:[0-9]+]]{{\]}}, [[VAL]], 31
250 ; GCN-NOT: v_lshl_b64
266 ; GCN-NOT: v_lshl_b64
281 ; GCN: v_lshl_b64
295 ; GCN: v_lshl_b64
307 ; GCN-DAG: v_lshl_b64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 3
308 ; GCN-DAG: v_lshl_b64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 4
309 ; GCN-DAG: v_lshl_b64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 5
310 ; GCN-DAG: v_lshl_b64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 6
Dshift-i128.ll9 ; GCN-NEXT: v_lshl_b64 v[5:6], v[2:3], v4
15 ; GCN-NEXT: v_lshl_b64 v[5:6], v[0:1], v5
17 ; GCN-NEXT: v_lshl_b64 v[0:1], v[0:1], v4
35 ; GCN-NEXT: v_lshl_b64 v[7:8], v[2:3], v7
61 ; GCN-NEXT: v_lshl_b64 v[7:8], v[2:3], v7
130 ; GCN-NEXT: v_lshl_b64 v[4:5], 17, v1
135 ; GCN-NEXT: v_lshl_b64 v[0:1], 17, v0
303 ; GCN-NEXT: v_lshl_b64 v[18:19], v[2:3], v8
311 ; GCN-NEXT: v_lshl_b64 v[16:17], v[0:1], v9
319 ; GCN-NEXT: v_lshl_b64 v[16:17], v[6:7], v12
[all …]
Dbitreverse.ll254 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 4
264 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
274 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
358 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 4
367 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
376 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
462 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 4
480 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
482 ; SI-NEXT: v_lshl_b64 v[4:5], v[4:5], 4
497 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
[all …]
Dudiv64.ll164 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0
179 ; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
181 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
214 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
376 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4
394 ; GCN-IR-NEXT: v_lshl_b64 v[12:13], v[12:13], 1
397 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
423 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[4:5], 1
874 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0
889 ; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
[all …]
Durem64.ll163 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0
178 ; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
180 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
213 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
385 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4
403 ; GCN-IR-NEXT: v_lshl_b64 v[14:15], v[14:15], 1
406 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
432 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
888 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], 24, v0
902 ; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
[all …]
Dllvm.amdgcn.s.barrier.ll23 ; VARIANT0-NEXT: v_lshl_b64 v[3:4], v[3:4], 2
43 ; VARIANT1-NEXT: v_lshl_b64 v[3:4], v[3:4], 2
Drotl.i64.ll21 ; SI-DAG: v_lshl_b64
Dsrem64.ll163 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0
178 ; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
180 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
213 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
410 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[0:1], v3
428 ; GCN-IR-NEXT: v_lshl_b64 v[16:17], v[16:17], 1
431 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
457 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
1071 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[8:9], v0
1086 ; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
[all …]
Dmad_64_32.ll86 ; CI: v_lshl_b64
100 ; CI: v_lshl_b64
Dsdiv64.ll190 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[10:11], v0
205 ; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
207 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
240 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
435 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[9:10], v0
453 ; GCN-IR-NEXT: v_lshl_b64 v[16:17], v[16:17], 1
456 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
482 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[7:8], 1
1061 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[10:11], v0
1076 ; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
[all …]
Drotr.i64.ll22 ; SI-DAG: v_lshl_b64
Dbfe-combine.ll35 ; CI: v_lshl_b64 v{{\[}}[[ADDRLO:[0-9]+]]:{{[^\]+}}], v{{\[}}[[AND]]:{{[^\]+}}], 2
Dsext-in-reg.ll153 ; SI: v_lshl_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}}
180 ; SI: v_lshl_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}}
207 ; SI: v_lshl_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}}
234 ; SI: v_lshl_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}},
464 ; SI: v_lshl_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}}
494 ; SI: v_lshl_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}},
Dshift-and-i128-ubfe.ll97 ; GCN-DAG: v_lshl_b64 v{{\[}}[[SHLLO:[0-9]+]]:[[SHLHI:[0-9]+]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, 30
Dfshr.ll815 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
818 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], v4
863 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
866 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], v8
867 ; SI-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
873 ; SI-NEXT: v_lshl_b64 v[2:3], v[2:3], v7
Dshl.ll616 ; GCN-NEXT: v_lshl_b64 v[0:1], v[0:1], v2
673 ; GCN-NEXT: v_lshl_b64 v[2:3], v[2:3], v6
674 ; GCN-NEXT: v_lshl_b64 v[0:1], v[0:1], v4
747 ; GCN-NEXT: v_lshl_b64 v[2:3], v[2:3], v10
749 ; GCN-NEXT: v_lshl_b64 v[6:7], v[6:7], v13
750 ; GCN-NEXT: v_lshl_b64 v[4:5], v[4:5], v11
751 ; GCN-NEXT: v_lshl_b64 v[0:1], v[0:1], v8
981 ; GCN-NEXT: v_lshl_b64 v[0:1], s[6:7], v0
1039 ; GCN-NEXT: v_lshl_b64 v[0:1], s[6:7], v0
1092 ; GCN-NEXT: v_lshl_b64 v[0:1], 64, v0
/external/llvm/test/CodeGen/AMDGPU/
Dshl.ll69 ;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
106 ;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
107 ;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
165 ;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
166 ;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
167 ;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
168 ;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
223 ; SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\]}}, s{{\[}}[[KLO]]:[[KHI]]{{\]}}, [[VAL]]
236 ; SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\]}}, s{{\[}}[[KLO]]:[[KHI]]{{\]}}, [[VAL]]
245 ; SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\]}}, 64, {{v[0-9]+}}
Drotl.i64.ll21 ; SI-DAG: v_lshl_b64
Drotr.i64.ll22 ; SI-DAG: v_lshl_b64
Dsext-in-reg.ll152 ; SI: v_lshl_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}}
173 ; SI: v_lshl_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}}
194 ; SI: v_lshl_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}}
215 ; SI: v_lshl_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}},
586 ; SI: v_lshl_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}}
611 ; SI: v_lshl_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}},
Dshift-and-i128-ubfe.ll95 ; GCN-DAG: v_lshl_b64 v{{\[}}[[SHLLO:[0-9]+]]:[[SHLHI:[0-9]+]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, 30
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dshl-ext-reduce.ll81 ; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
124 ; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
155 ; GFX7-NEXT: v_lshl_b64 v[2:3], v[0:1], 2
218 ; GFX7-NEXT: v_lshl_b64 v[0:1], v[1:2], 3
302 ; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
303 ; GFX7-NEXT: v_lshl_b64 v[2:3], v[2:3], 2
362 ; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
363 ; GFX7-NEXT: v_lshl_b64 v[2:3], v[2:3], 2
Dmubuf-global.ll378 ; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
390 ; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
407 ; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
420 ; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
439 ; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
451 ; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
834 ; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
846 ; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
863 ; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
876 ; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
[all …]
Dshl.ll966 ; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], v2
1021 ; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 31
1090 ; GFX6-NEXT: v_lshl_b64 v[0:1], s[0:1], v0
1110 ; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], s0
1131 ; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], v4
1132 ; GFX6-NEXT: v_lshl_b64 v[2:3], v[2:3], v6
1156 ; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 31
1157 ; GFX6-NEXT: v_lshl_b64 v[2:3], v[2:3], 31
Dxnor.ll230 ; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 29
274 ; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 29

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