| /external/capstone/suite/MC/ARM/ |
| D | neon-cmp-encoding.s.cs | 2 0xb1,0x08,0x40,0xf3 = vceq.i8 d16, d16, d17
3 0xb1,0x08,0x50,0xf3 = vceq.i16 d16, d16, d17
4 0xb1,0x08,0x60,0xf3 = vceq.i32 d16, d16, d17
5 0xa1,0x0e,0x40,0xf2 = vceq.f32 d16, d16, d17
6 0xf2,0x08,0x40,0xf3 = vceq.i8 q8, q8, q9
7 0xf2,0x08,0x50,0xf3 = vceq.i16 q8, q8, q9
8 0xf2,0x08,0x60,0xf3 = vceq.i32 q8, q8, q9
9 0xe2,0x0e,0x40,0xf2 = vceq.f32 q8, q8, q9
48 0x20,0x01,0xf1,0xf3 = vceq.i8 d16, d16, #0
|
| D | neon-bitwise-encoding.s.cs | 109 0x56,0xa8,0x1a,0xf3 = vceq.i16 q5, q5, q3
110 0x13,0x58,0x15,0xf3 = vceq.i16 d5, d5, d3
119 0x4a,0xa1,0xb5,0xf3 = vceq.i16 q5, q5, #0
120 0x05,0x51,0xb5,0xf3 = vceq.i16 d5, d5, #0
|
| /external/llvm-project/llvm/test/MC/ARM/ |
| D | neon-cmp-encoding.s | 3 vceq.i8 d16, d16, d17
4 vceq.i16 d16, d16, d17
5 vceq.i32 d16, d16, d17
6 vceq.f32 d16, d16, d17
7 vceq.i8 q8, q8, q9
8 vceq.i16 q8, q8, q9
9 vceq.i32 q8, q8, q9
10 vceq.f32 q8, q8, q9
12 @ CHECK: vceq.i8 d16, d16, d17 @ encoding: [0xb1,0x08,0x40,0xf3]
13 @ CHECK: vceq.i16 d16, d16, d17 @ encoding: [0xb1,0x08,0x50,0xf3]
[all …]
|
| D | fullfp16-neon.s | 74 vceq.f16 d2, d3, d4
75 vceq.f16 q2, q3, q4
76 @ ARM: vceq.f16 d2, d3, d4 @ encoding: [0x04,0x2e,0x13,0xf2]
77 @ ARM: vceq.f16 q2, q3, q4 @ encoding: [0x48,0x4e,0x16,0xf2]
78 @ THUMB: vceq.f16 d2, d3, d4 @ encoding: [0x13,0xef,0x04,0x2e]
79 @ THUMB: vceq.f16 q2, q3, q4 @ encoding: [0x16,0xef,0x48,0x4e]
81 vceq.f16 d2, d3, #0
82 vceq.f16 q2, q3, #0
83 @ ARM: vceq.f16 d2, d3, #0 @ encoding: [0x03,0x25,0xb5,0xf3]
84 @ ARM: vceq.f16 q2, q3, #0 @ encoding: [0x46,0x45,0xb5,0xf3]
[all …]
|
| D | neon-bitwise-encoding.s | 314 vceq.s16 q5, q3
315 vceq.s16 d5, d3
329 vceq.s16 q5, #0
330 vceq.s16 d5, #0
|
| D | fullfp16-neon-neg.s | 56 vceq.f16 d2, d3, d4
57 vceq.f16 q2, q3, q4
61 vceq.f16 d2, d3, #0
62 vceq.f16 q2, q3, #0
|
| /external/llvm/test/MC/ARM/ |
| D | neon-cmp-encoding.s | 3 vceq.i8 d16, d16, d17
4 vceq.i16 d16, d16, d17
5 vceq.i32 d16, d16, d17
6 vceq.f32 d16, d16, d17
7 vceq.i8 q8, q8, q9
8 vceq.i16 q8, q8, q9
9 vceq.i32 q8, q8, q9
10 vceq.f32 q8, q8, q9
12 @ CHECK: vceq.i8 d16, d16, d17 @ encoding: [0xb1,0x08,0x40,0xf3]
13 @ CHECK: vceq.i16 d16, d16, d17 @ encoding: [0xb1,0x08,0x50,0xf3]
[all …]
|
| D | fullfp16-neon.s | 74 vceq.f16 d2, d3, d4
75 vceq.f16 q2, q3, q4
76 @ ARM: vceq.f16 d2, d3, d4 @ encoding: [0x04,0x2e,0x13,0xf2]
77 @ ARM: vceq.f16 q2, q3, q4 @ encoding: [0x48,0x4e,0x16,0xf2]
78 @ THUMB: vceq.f16 d2, d3, d4 @ encoding: [0x13,0xef,0x04,0x2e]
79 @ THUMB: vceq.f16 q2, q3, q4 @ encoding: [0x16,0xef,0x48,0x4e]
81 vceq.f16 d2, d3, #0
82 vceq.f16 q2, q3, #0
83 @ ARM: vceq.f16 d2, d3, #0 @ encoding: [0x03,0x25,0xb5,0xf3]
84 @ ARM: vceq.f16 q2, q3, #0 @ encoding: [0x46,0x45,0xb5,0xf3]
[all …]
|
| D | fullfp16-neon-neg.s | 56 vceq.f16 d2, d3, d4
57 vceq.f16 q2, q3, q4
61 vceq.f16 d2, d3, #0
62 vceq.f16 q2, q3, #0
|
| D | neon-bitwise-encoding.s | 307 vceq.s16 q5, q3
308 vceq.s16 d5, d3
322 vceq.s16 q5, #0
323 vceq.s16 d5, #0
|
| /external/llvm/test/CodeGen/ARM/ |
| D | vceq.ll | 5 ;CHECK: vceq.i8
15 ;CHECK: vceq.i16
25 ;CHECK: vceq.i32
35 ;CHECK: vceq.f32
45 ;CHECK: vceq.i8
55 ;CHECK: vceq.i16
65 ;CHECK: vceq.i32
75 ;CHECK: vceq.f32
87 ;CHECK: vceq.i8
|
| D | vicmp.ll | 11 ;CHECK: vceq.i8
22 ;CHECK: vceq.i16
33 ;CHECK: vceq.i32
44 ;CHECK: vceq.i8
55 ;CHECK: vceq.i16
66 ;CHECK: vceq.i32
|
| D | setcc-type-mismatch.ll | 5 ; CHECK: vceq.i32 [[CMP128:q[0-9]+]], {{q[0-9]+}}, {{q[0-9]+}}
|
| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | vceq.ll | 9 ; CHECK-NEXT: vceq.i8 d16, d17, d16
24 ; CHECK-NEXT: vceq.i16 d16, d17, d16
39 ; CHECK-NEXT: vceq.i32 d16, d17, d16
54 ; CHECK-NEXT: vceq.f32 d16, d17, d16
69 ; CHECK-NEXT: vceq.i8 q8, q9, q8
85 ; CHECK-NEXT: vceq.i16 q8, q9, q8
101 ; CHECK-NEXT: vceq.i32 q8, q9, q8
117 ; CHECK-NEXT: vceq.f32 q8, q9, q8
132 ; CHECK-NEXT: vceq.i8 d16, d16, #0
|
| D | vicmp.ll | 11 ;CHECK: vceq.i8
22 ;CHECK: vceq.i16
33 ;CHECK: vceq.i32
44 ;CHECK: vceq.i8
55 ;CHECK: vceq.i16
66 ;CHECK: vceq.i32
|
| D | vicmp-64.ll | 8 ;CHECK: vceq.i32
24 ;CHECK: vceq.i32
|
| D | setcc-type-mismatch.ll | 5 ; CHECK: vceq.i32 [[CMP128:q[0-9]+]], {{q[0-9]+}}, {{q[0-9]+}}
|
| D | setcc-logic.ll | 61 ; CHECK-NEXT: vceq.i32 q8, q9, q8
63 ; CHECK-NEXT: vceq.i32 q9, q11, q10
|
| /external/arm-neon-tests/ |
| D | ref_vceq.c | 26 #define INSN_NAME vceq
|
| D | Makefile.gcc | 46 vqsub vqdmulh_lane vqdmull vqdmlal vqdmlsl vceq vcge vcle \
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | fullfp16-neon-arm.txt | 54 # CHECK: vceq.f16 d2, d3, d4
55 # CHECK: vceq.f16 q2, q3, q4
59 # CHECK: vceq.f16 d2, d3, #0
60 # CHECK: vceq.f16 q2, q3, #0
|
| D | fullfp16-neon-thumb.txt | 54 # CHECK: vceq.f16 d2, d3, d4
55 # CHECK: vceq.f16 q2, q3, q4
59 # CHECK: vceq.f16 d2, d3, #0
60 # CHECK: vceq.f16 q2, q3, #0
|
| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | fullfp16-neon-thumb.txt | 54 # CHECK: vceq.f16 d2, d3, d4
55 # CHECK: vceq.f16 q2, q3, q4
59 # CHECK: vceq.f16 d2, d3, #0
60 # CHECK: vceq.f16 q2, q3, #0
|
| D | fullfp16-neon-arm.txt | 54 # CHECK: vceq.f16 d2, d3, d4
55 # CHECK: vceq.f16 q2, q3, q4
59 # CHECK: vceq.f16 d2, d3, #0
60 # CHECK: vceq.f16 q2, q3, #0
|
| /external/libavc/common/arm/ |
| D | ih264_resi_trans_quant_a9.s | 215 vceq.s16 q5, q15, #0 @I compare with zero row 1 and 2 blk 1
216 vceq.s16 q6, q0 , #0 @I compare with zero row 1 and 2 blk 1
410 vceq.s16 q5, q15, #0 @I compare with zero row 1 and 2 blk 1
411 vceq.s16 q6, q0 , #0 @I compare with zero row 1 and 2 blk 1
557 vceq.s16 q5, q11, #0
558 vceq.s16 q6, q12, #0
673 vceq.s16 q7, q4, #0 @Compute nnz
|