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Searched refs:vgprs (Results 1 – 20 of 20) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dmadak-inline-constant.mir65 name: test src1-2vgprs-inlined
84 name: test src0-2vgprs-inlined
Dmfma-loop.ll7 ; Check that we do not copy agprs to vgprs and back inside the loop.
38 ; Check that we do not use 32 temp vgprs, but rotate 3 vgprs only.
39 ; 3 vgprs are needed to avoid wait states between writes.
103 ; Check that we do not use 32 temp vgprs, but rotate 3 vgprs only.
104 ; 3 vgprs are needed to avoid wait states between writes.
494 ; Check that we do not copy agprs to vgprs and back in an outer loop.
Dwave_dispatch_regs.ll5 ; This compute shader has input args that claim that it has 17 sgprs and 5 vgprs
Dsalu-to-valu.ll9 ; BUFFER_LOAD instructions end up being stored in vgprs. This
Dsgpr-copy.ll314 ; vgprs. The verifier will fail if this happens.
Dfunction-args.ll499 ; Make sure there is no alignment requirement for passed vgprs.
/external/mesa3d/src/amd/compiler/
Daco_live_var_analysis.cpp317 uint16_t vgprs = 256 / max_waves & ~program->vgpr_alloc_granule; in get_addr_vgpr_from_waves() local
318 return std::min(vgprs, program->vgpr_limit); in get_addr_vgpr_from_waves()
Daco_spill.cpp1732 std::set<Temp> vgprs; in assign_spill_slots() local
1741 vgprs.insert(pred_instr->operands[0].getTemp()); in assign_spill_slots()
1745 if (!vgprs.size()) in assign_spill_slots()
1748 …e_instruction<Pseudo_instruction>(aco_opcode::p_end_linear_vgpr, Format::PSEUDO, vgprs.size(), 0)}; in assign_spill_slots()
1750 for (Temp tmp : vgprs) { in assign_spill_slots()
Daco_register_allocation.cpp255 void print_regs(ra_ctx& ctx, bool vgprs, RegisterFile& reg_file)
257 unsigned max = vgprs ? ctx.program->max_reg_demand.vgpr : ctx.program->max_reg_demand.sgpr;
258 unsigned lb = vgprs ? 256 : 0;
260 char reg_char = vgprs ? 'v' : 's';
/external/llvm/lib/Target/AMDGPU/Utils/
DAMDKernelCodeTInfo.h99 COMPPGM1(vgprs, VGPRS),
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSISchedule.td142 // need to consume 2 or 4 more vgprs to be initialized before the acc
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSISchedule.td159 // need to consume 2 or 4 more vgprs to be initialized before the acc
/external/mesa3d/src/amd/vulkan/
Dradv_shader.c1556 unsigned vgprs = align(conf->num_vgprs, wave_size == 32 ? 8 : 4); in radv_get_max_waves() local
1559 device->physical_device->rad_info.num_physical_wave64_vgprs_per_simd / vgprs); in radv_get_max_waves()
/external/llvm/test/CodeGen/AMDGPU/
Dsalu-to-valu.ll9 ; BUFFER_LOAD instructions end up being stored in vgprs. This
Dsgpr-copy.ll319 ; vgprs. The verifier will fail if this happens.
/external/mesa3d/docs/relnotes/
D19.3.0.rst2857 - radv: round vgprs/sgprs before calculating max_waves
2868 - aco: don't propagate vgprs into v_readlane/v_writelane
D20.0.0.rst2768 - aco: don't propagate vgprs into v_readlane/v_writelane
D20.2.0.rst3800 - aco: fix consecutively written vgprs from vmem instructions
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dirtranslator-function-args.ll1628 ; Make sure there is no alignment requirement for passed vgprs.
/external/llvm-project/llvm/docs/
DAMDGPUUsage.rst4067 … compute_pgm_rsrc1.vgprs + shared_vgpr_cnt cannot exceed 64.