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Searched refs:vlr (Results 1 – 25 of 33) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/SystemZ/
Dvec-move-01.ll8 ; CHECK: vlr %v24, %v26
16 ; CHECK: vlr %v24, %v26
24 ; CHECK: vlr %v24, %v26
32 ; CHECK: vlr %v24, %v26
40 ; CHECK: vlr %v24, %v26
48 ; CHECK: vlr %v24, %v26
56 ; CHECK: vlr %v24, %v26
64 ; CHECK: vlr %v24, %v26
72 ; CHECK: vlr %v24, %v26
80 ; CHECK: vlr %v24, %v26
[all …]
Dvec-move-07.ll44 ; CHECK: vlr %v24, %v0
53 ; CHECK: vlr %v24, %v0
Dasm-19.ll123 ; CHECK: vlr %v24, %v4
131 ; CHECK: vlr [[REG:%v[0-9]+]], %v24
133 ; CHECK: vlr %v24, [[REG]]
Dfp-move-13.ll9 ; CHECK: vlr
Dvec-sub-01.ll47 ; CHECK-DAG: vlr %v[[A1:[0-5]]], %v24
48 ; CHECK-DAG: vlr %v[[A2:[0-5]]], %v26
Dvec-args-07.ll14 ; CHECK: vlr %v24, %v31
Dvec-move-05.ll156 ; CHECK: vlr %v0, %v24
209 ; CHECK: vlr %v0, %v24
Dvector-constrained-fp-intrinsics.ll19 ; SZ13-NEXT: vlr %v24, %v0
209 ; SZ13-NEXT: vlr %v24, %v0
574 ; SZ13-NEXT: vlr %v24, %v1
748 ; SZ13-NEXT: vlr %v24, %v1
920 ; SZ13-NEXT: vlr %v24, %v1
1089 ; SZ13-NEXT: vlr %v24, %v0
1244 ; SZ13-NEXT: vlr %v24, %v0
1633 ; SZ13-NEXT: vlr %v24, %v0
1974 ; SZ13-NEXT: vlr %v24, %v0
2291 ; SZ13-NEXT: vlr %v24, %v0
[all …]
/external/llvm/test/CodeGen/SystemZ/
Dvec-move-01.ll8 ; CHECK: vlr %v24, %v26
16 ; CHECK: vlr %v24, %v26
24 ; CHECK: vlr %v24, %v26
32 ; CHECK: vlr %v24, %v26
40 ; CHECK: vlr %v24, %v26
48 ; CHECK: vlr %v24, %v26
56 ; CHECK: vlr %v24, %v26
64 ; CHECK: vlr %v24, %v26
72 ; CHECK: vlr %v24, %v26
80 ; CHECK: vlr %v24, %v26
[all …]
Dvec-move-07.ll44 ; CHECK: vlr %v24, %v0
53 ; CHECK: vlr %v24, %v0
Dvec-args-07.ll12 ; CHECK: vlr %v24, %v31
Dvec-sub-01.ll47 ; CHECK-DAG: vlr %v[[A1:[0-5]]], %v24
48 ; CHECK-DAG: vlr %v[[A2:[0-5]]], %v26
Dvec-move-05.ll156 ; CHECK: vlr %v0, %v24
209 ; CHECK: vlr %v0, %v24
/external/llvm-project/llvm/test/MC/SystemZ/
Ddirective-insn-vector.s20 #CHECK: e7 37 00 00 00 56 vlr %v3, %v7
28 #CHECK: e7 01 00 00 0c 56 vlr %v16, %v17
Dinsn-good-z13.s3870 #CHECK: vlr %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x56]
3871 #CHECK: vlr %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x56]
3872 #CHECK: vlr %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x56]
3873 #CHECK: vlr %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x56]
3874 #CHECK: vlr %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x56]
3875 #CHECK: vlr %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x04,0x56]
3877 vlr %v0, %v0
3878 vlr %v0, %v15
3879 vlr %v0, %v31
3880 vlr %v15, %v0
[all …]
/external/XNNPACK/src/f32-ibilinear-chw/gen/
Dwasmsimd-p4.c148 const v128_t vlr = wasm_f32x4_add(vtltr, wasm_f32x4_mul(vldrd, valphav)); in xnn_f32_ibilinear_chw_ukernel__wasmsimd_p4() local
151 const float l = wasm_f32x4_extract_lane(vlr, 0); in xnn_f32_ibilinear_chw_ukernel__wasmsimd_p4()
152 const float r = wasm_f32x4_extract_lane(vlr, 1); in xnn_f32_ibilinear_chw_ukernel__wasmsimd_p4()
Dneonfma-p4.c155 const float32x2_t vlr = vfma_f32(vtltr, vldrd, valphav); in xnn_f32_ibilinear_chw_ukernel__neonfma_p4() local
158 const float l = vget_lane_f32(vlr, 0); in xnn_f32_ibilinear_chw_ukernel__neonfma_p4()
159 const float r = vget_lane_f32(vlr, 1); in xnn_f32_ibilinear_chw_ukernel__neonfma_p4()
Dneon-p4.c155 const float32x2_t vlr = vmla_f32(vtltr, vldrd, valphav); in xnn_f32_ibilinear_chw_ukernel__neon_p4() local
158 const float l = vget_lane_f32(vlr, 0); in xnn_f32_ibilinear_chw_ukernel__neon_p4()
159 const float r = vget_lane_f32(vlr, 1); in xnn_f32_ibilinear_chw_ukernel__neon_p4()
Dwasmsimd-p8.c234 const v128_t vlr = wasm_f32x4_add(vtltr, wasm_f32x4_mul(vldrd, valphav)); in xnn_f32_ibilinear_chw_ukernel__wasmsimd_p8() local
237 const float l = wasm_f32x4_extract_lane(vlr, 0); in xnn_f32_ibilinear_chw_ukernel__wasmsimd_p8()
238 const float r = wasm_f32x4_extract_lane(vlr, 1); in xnn_f32_ibilinear_chw_ukernel__wasmsimd_p8()
Dneonfma-p8.c243 const float32x2_t vlr = vfma_f32(vtltr, vldrd, valphav); in xnn_f32_ibilinear_chw_ukernel__neonfma_p8() local
246 const float l = vget_lane_f32(vlr, 0); in xnn_f32_ibilinear_chw_ukernel__neonfma_p8()
247 const float r = vget_lane_f32(vlr, 1); in xnn_f32_ibilinear_chw_ukernel__neonfma_p8()
Dneon-p8.c243 const float32x2_t vlr = vmla_f32(vtltr, vldrd, valphav); in xnn_f32_ibilinear_chw_ukernel__neon_p8() local
246 const float l = vget_lane_f32(vlr, 0); in xnn_f32_ibilinear_chw_ukernel__neon_p8()
247 const float r = vget_lane_f32(vlr, 1); in xnn_f32_ibilinear_chw_ukernel__neon_p8()
/external/XNNPACK/src/f32-ibilinear-chw/
Dwasmsimd.c.in188 const v128_t vlr = wasm_f32x4_add(vtltr, wasm_f32x4_mul(vldrd, valphav)); variable
191 const float l = wasm_f32x4_extract_lane(vlr, 0);
192 const float r = wasm_f32x4_extract_lane(vlr, 1);
Dneon.c.in193 const float32x2_t vlr = ${VMULADD_F32}(vtltr, vldrd, valphav);
196 const float l = vget_lane_f32(vlr, 0);
197 const float r = vget_lane_f32(vlr, 1);
/external/llvm/test/MC/SystemZ/
Dinsn-good-z13.s2415 #CHECK: vlr %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x56]
2416 #CHECK: vlr %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x56]
2417 #CHECK: vlr %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x56]
2418 #CHECK: vlr %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x56]
2419 #CHECK: vlr %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x56]
2420 #CHECK: vlr %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x04,0x56]
2422 vlr %v0, %v0
2423 vlr %v0, %v15
2424 vlr %v0, %v31
2425 vlr %v15, %v0
[all …]
/external/cldr/tools/java/org/unicode/cldr/util/data/
Diso-639-3_Retirements.tab159 vlr Vatrata S Split into Vera'a [vra] and Lemerig [lrz] 2009-01-16

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