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/external/llvm-project/llvm/test/MC/ARM/
Dneon-reciprocal-encoding.s23 @ CHECK: vrsqrts.f32 d16, d16, d17 @ encoding: [0xb1,0x0f,0x60,0xf2]
24 vrsqrts.f32 d16, d16, d17
25 @ CHECK: vrsqrts.f32 q8, q8, q9 @ encoding: [0xf2,0x0f,0x60,0xf2]
26 vrsqrts.f32 q8, q8, q9
Dneont2-reciprocal-encoding.s25 @ CHECK: vrsqrts.f32 d16, d16, d17 @ encoding: [0x60,0xef,0xb1,0x0f]
26 vrsqrts.f32 d16, d16, d17
27 @ CHECK: vrsqrts.f32 q8, q8, q9 @ encoding: [0x60,0xef,0xf2,0x0f]
28 vrsqrts.f32 q8, q8, q9
Dfullfp16-neon.s247 vrsqrts.f16 d0, d1, d2
248 vrsqrts.f16 q0, q1, q2
249 @ ARM: vrsqrts.f16 d0, d1, d2 @ encoding: [0x12,0x0f,0x31,0xf2]
250 @ ARM: vrsqrts.f16 q0, q1, q2 @ encoding: [0x54,0x0f,0x32,0xf2]
251 @ THUMB: vrsqrts.f16 d0, d1, d2 @ encoding: [0x31,0xef,0x12,0x0f]
252 @ THUMB: vrsqrts.f16 q0, q1, q2 @ encoding: [0x32,0xef,0x54,0x0f]
Dfullfp16-neon-neg.s180 vrsqrts.f16 d0, d1, d2
181 vrsqrts.f16 q0, q1, q2
/external/llvm/test/MC/ARM/
Dneon-reciprocal-encoding.s23 @ CHECK: vrsqrts.f32 d16, d16, d17 @ encoding: [0xb1,0x0f,0x60,0xf2]
24 vrsqrts.f32 d16, d16, d17
25 @ CHECK: vrsqrts.f32 q8, q8, q9 @ encoding: [0xf2,0x0f,0x60,0xf2]
26 vrsqrts.f32 q8, q8, q9
Dneont2-reciprocal-encoding.s25 @ CHECK: vrsqrts.f32 d16, d16, d17 @ encoding: [0x60,0xef,0xb1,0x0f]
26 vrsqrts.f32 d16, d16, d17
27 @ CHECK: vrsqrts.f32 q8, q8, q9 @ encoding: [0x60,0xef,0xf2,0x0f]
28 vrsqrts.f32 q8, q8, q9
Dfullfp16-neon.s247 vrsqrts.f16 d0, d1, d2
248 vrsqrts.f16 q0, q1, q2
249 @ ARM: vrsqrts.f16 d0, d1, d2 @ encoding: [0x12,0x0f,0x31,0xf2]
250 @ ARM: vrsqrts.f16 q0, q1, q2 @ encoding: [0x54,0x0f,0x32,0xf2]
251 @ THUMB: vrsqrts.f16 d0, d1, d2 @ encoding: [0x31,0xef,0x12,0x0f]
252 @ THUMB: vrsqrts.f16 q0, q1, q2 @ encoding: [0x32,0xef,0x54,0x0f]
Dfullfp16-neon-neg.s180 vrsqrts.f16 d0, d1, d2
181 vrsqrts.f16 q0, q1, q2
/external/llvm-project/llvm/test/CodeGen/ARM/
Dvrec.ll102 ;CHECK: vrsqrts.f32
105 %tmp3 = call <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
111 ;CHECK: vrsqrts.f32
114 %tmp3 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
118 declare <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float>, <2 x float>) nounwind readnone
119 declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone
D2009-11-01-NeonMoves.ll25 …%10 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %9, <4 x float> %7) nounwind ; <<4…
40 declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone
Darmv8.2a-fp16-vector-intrinsics.ll908 ; CHECK: vrsqrts.f16 d0, d0, d1
911 %vrsqrts_v2.i = tail call <4 x half> @llvm.arm.neon.vrsqrts.v4f16(<4 x half> %a, <4 x half> %b)
917 ; CHECK: vrsqrts.f16 q0, q0, q1
920 %vrsqrtsq_v2.i = tail call <8 x half> @llvm.arm.neon.vrsqrts.v8f16(<8 x half> %a, <8 x half> %b)
1316 declare <4 x half> @llvm.arm.neon.vrsqrts.v4f16(<4 x half>, <4 x half>)
1317 declare <8 x half> @llvm.arm.neon.vrsqrts.v8f16(<8 x half>, <8 x half>)
/external/llvm/test/CodeGen/ARM/
Dvrec.ll102 ;CHECK: vrsqrts.f32
105 %tmp3 = call <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
111 ;CHECK: vrsqrts.f32
114 %tmp3 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
118 declare <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float>, <2 x float>) nounwind readnone
119 declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone
D2009-11-01-NeonMoves.ll25 …%10 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %9, <4 x float> %7) nounwind ; <<4…
40 declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone
/external/capstone/suite/MC/ARM/
Dneon-reciprocal-encoding.s.cs12 0xb1,0x0f,0x60,0xf2 = vrsqrts.f32 d16, d16, d17
13 0xf2,0x0f,0x60,0xf2 = vrsqrts.f32 q8, q8, q9
Dneont2-reciprocal-encoding.s.cs12 0x60,0xef,0xb1,0x0f = vrsqrts.f32 d16, d16, d17
13 0x60,0xef,0xf2,0x0f = vrsqrts.f32 q8, q8, q9
/external/llvm-project/llvm/test/CodeGen/VE/VELIntrinsics/
Dvrsqrt.ll50 %2 = tail call fast <256 x double> @llvm.ve.vl.vrsqrts.vvl(<256 x double> %0, i32 256)
55 declare <256 x double> @llvm.ve.vl.vrsqrts.vvl(<256 x double>, i32)
68 …%3 = tail call fast <256 x double> @llvm.ve.vl.vrsqrts.vvvl(<256 x double> %0, <256 x double> %1, …
73 declare <256 x double> @llvm.ve.vl.vrsqrts.vvvl(<256 x double>, <256 x double>, i32)
/external/arm-neon-tests/
Dref_vrsqrts.c43 vrsqrts##Q##_##T2##W(VECT_VAR(vector, T1, W, N), \ in exec_vrsqrts()
DMakefile.gcc61 vcalt vrecps vrsqrts vcvt
DMakefile55 vcalt vrecps vrsqrts vcvt
/external/llvm/test/MC/Disassembler/ARM/
Dfullfp16-neon-arm.txt158 # CHECK: vrsqrts.f16 d0, d1, d2
159 # CHECK: vrsqrts.f16 q0, q1, q2
Dfullfp16-neon-thumb.txt158 # CHECK: vrsqrts.f16 d0, d1, d2
159 # CHECK: vrsqrts.f16 q0, q1, q2
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dfullfp16-neon-thumb.txt158 # CHECK: vrsqrts.f16 d0, d1, d2
159 # CHECK: vrsqrts.f16 q0, q1, q2
Dfullfp16-neon-arm.txt158 # CHECK: vrsqrts.f16 d0, d1, d2
159 # CHECK: vrsqrts.f16 q0, q1, q2
/external/llvm-project/clang/include/clang/Basic/
Darm_fp16.td25 def SCALAR_FRSQRTSH : IInst<"vrsqrts", "111", "Sh">;
Darm_neon.td394 def VRSQRTS : IInst<"vrsqrts", "...", "fQf">;
818 def FRSQRTS : IInst<"vrsqrts", "...", "dQd">;
1372 def SCALAR_FRSQRTS : IInst<"vrsqrts", "111", "SfSd">;
1695 def VRSQRTSH : SInst<"vrsqrts", "...", "hQh">;

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