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1 /*
2  * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef IMX_USDHC_H
8 #define IMX_USDHC_H
9 
10 #include <drivers/mmc.h>
11 
12 typedef struct imx_usdhc_params {
13 	uintptr_t	reg_base;
14 	int		clk_rate;
15 	int		bus_width;
16 	unsigned int	flags;
17 } imx_usdhc_params_t;
18 
19 void imx_usdhc_init(imx_usdhc_params_t *params,
20 		    struct mmc_device_info *mmc_dev_info);
21 
22 /* iMX MMC registers definition */
23 #define DSADDR			0x000
24 #define BLKATT			0x004
25 #define CMDARG			0x008
26 #define CMDRSP0			0x010
27 #define CMDRSP1			0x014
28 #define CMDRSP2			0x018
29 #define CMDRSP3			0x01c
30 
31 #define XFERTYPE		0x00c
32 #define XFERTYPE_CMD(x)		(((x) & 0x3f) << 24)
33 #define XFERTYPE_CMDTYP_ABORT	(3 << 22)
34 #define XFERTYPE_DPSEL		BIT(21)
35 #define XFERTYPE_CICEN		BIT(20)
36 #define XFERTYPE_CCCEN		BIT(19)
37 #define XFERTYPE_RSPTYP_136	BIT(16)
38 #define XFERTYPE_RSPTYP_48	BIT(17)
39 #define XFERTYPE_RSPTYP_48_BUSY	(BIT(16) | BIT(17))
40 
41 #define PSTATE			0x024
42 #define PSTATE_DAT0		BIT(24)
43 #define PSTATE_DLA		BIT(2)
44 #define PSTATE_CDIHB		BIT(1)
45 #define PSTATE_CIHB		BIT(0)
46 
47 #define PROTCTRL		0x028
48 #define PROTCTRL_LE		BIT(5)
49 #define PROTCTRL_WIDTH_4	BIT(1)
50 #define PROTCTRL_WIDTH_8	BIT(2)
51 #define PROTCTRL_WIDTH_MASK	0x6
52 
53 #define SYSCTRL			0x02c
54 #define SYSCTRL_RSTD		BIT(26)
55 #define SYSCTRL_RSTC		BIT(25)
56 #define SYSCTRL_RSTA		BIT(24)
57 #define SYSCTRL_CLOCK_MASK	0x0000fff0
58 #define SYSCTRL_TIMEOUT_MASK	0x000f0000
59 #define SYSCTRL_TIMEOUT(x)	((0xf & (x)) << 16)
60 
61 #define INTSTAT			0x030
62 #define INTSTAT_DMAE		BIT(28)
63 #define INTSTAT_DEBE		BIT(22)
64 #define INTSTAT_DCE		BIT(21)
65 #define INTSTAT_DTOE		BIT(20)
66 #define INTSTAT_CIE		BIT(19)
67 #define INTSTAT_CEBE		BIT(18)
68 #define INTSTAT_CCE		BIT(17)
69 #define INTSTAT_DINT		BIT(3)
70 #define INTSTAT_BGE		BIT(2)
71 #define INTSTAT_TC		BIT(1)
72 #define INTSTAT_CC		BIT(0)
73 #define CMD_ERR			(INTSTAT_CIE | INTSTAT_CEBE | INTSTAT_CCE)
74 #define DATA_ERR		(INTSTAT_DMAE | INTSTAT_DEBE | INTSTAT_DCE | \
75 				 INTSTAT_DTOE)
76 #define DATA_COMPLETE		(INTSTAT_DINT | INTSTAT_TC)
77 
78 #define INTSTATEN		0x034
79 #define INTSTATEN_DEBE		BIT(22)
80 #define INTSTATEN_DCE		BIT(21)
81 #define INTSTATEN_DTOE		BIT(20)
82 #define INTSTATEN_CIE		BIT(19)
83 #define INTSTATEN_CEBE		BIT(18)
84 #define INTSTATEN_CCE		BIT(17)
85 #define INTSTATEN_CTOE		BIT(16)
86 #define INTSTATEN_CINT		BIT(8)
87 #define INTSTATEN_BRR		BIT(5)
88 #define INTSTATEN_BWR		BIT(4)
89 #define INTSTATEN_DINT		BIT(3)
90 #define INTSTATEN_TC		BIT(1)
91 #define INTSTATEN_CC		BIT(0)
92 #define EMMC_INTSTATEN_BITS	(INTSTATEN_CC | INTSTATEN_TC | INTSTATEN_DINT | \
93 				 INTSTATEN_BWR | INTSTATEN_BRR | INTSTATEN_CINT | \
94 				 INTSTATEN_CTOE | INTSTATEN_CCE | INTSTATEN_CEBE | \
95 				 INTSTATEN_CIE | INTSTATEN_DTOE | INTSTATEN_DCE | \
96 				 INTSTATEN_DEBE)
97 
98 #define INTSIGEN		0x038
99 
100 #define WATERMARKLEV		0x044
101 #define WMKLV_RD_MASK		0xff
102 #define WMKLV_WR_MASK		0x00ff0000
103 #define WMKLV_MASK		(WMKLV_RD_MASK | WMKLV_WR_MASK)
104 
105 #define MIXCTRL			0x048
106 #define MIXCTRL_MSBSEL		BIT(5)
107 #define MIXCTRL_DTDSEL		BIT(4)
108 #define MIXCTRL_DDREN		BIT(3)
109 #define MIXCTRL_AC12EN		BIT(2)
110 #define MIXCTRL_BCEN		BIT(1)
111 #define MIXCTRL_DMAEN		BIT(0)
112 #define MIXCTRL_DATMASK		0x7f
113 
114 #define DLLCTRL			0x060
115 
116 #define CLKTUNECTRLSTS		0x068
117 
118 #define VENDSPEC		0x0c0
119 #define VENDSPEC_RSRV1		BIT(29)
120 #define VENDSPEC_CARD_CLKEN	BIT(14)
121 #define VENDSPEC_PER_CLKEN	BIT(13)
122 #define VENDSPEC_AHB_CLKEN	BIT(12)
123 #define VENDSPEC_IPG_CLKEN	BIT(11)
124 #define VENDSPEC_AC12_CHKBUSY	BIT(3)
125 #define VENDSPEC_EXTDMA		BIT(0)
126 #define VENDSPEC_INIT		(VENDSPEC_RSRV1	| VENDSPEC_CARD_CLKEN | \
127 				 VENDSPEC_PER_CLKEN | VENDSPEC_AHB_CLKEN | \
128 				 VENDSPEC_IPG_CLKEN | VENDSPEC_AC12_CHKBUSY | \
129 				 VENDSPEC_EXTDMA)
130 
131 #define MMCBOOT			0x0c4
132 
133 #define mmio_clrsetbits32(addr, clear, set)	mmio_write_32(addr, (mmio_read_32(addr) & ~(clear)) | (set))
134 #define mmio_clrbits32(addr, clear)		mmio_write_32(addr, mmio_read_32(addr) & ~(clear))
135 #define mmio_setbits32(addr, set)		mmio_write_32(addr, mmio_read_32(addr) | (set))
136 
137 #endif /* IMX_USDHC_H */
138