1 /*
2 * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights
3 * reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <stddef.h>
9
10 #include <lib/mmio.h>
11
12 #include "emmc_config.h"
13 #include "emmc_def.h"
14 #include "emmc_hal.h"
15 #include "emmc_registers.h"
16 #include "emmc_std.h"
17 #include "rcar_def.h"
18
19 static EMMC_ERROR_CODE emmc_trans_sector(uint32_t *buff_address_virtual);
20
emmc_interrupt(void)21 uint32_t emmc_interrupt(void)
22 {
23 EMMC_ERROR_CODE result;
24 uint32_t prr_data;
25 uint32_t cut_ver;
26 uint32_t end_bit;
27
28 prr_data = mmio_read_32((uintptr_t) RCAR_PRR);
29 cut_ver = prr_data & PRR_CUT_MASK;
30 if ((prr_data & PRR_PRODUCT_MASK) == PRR_PRODUCT_H3) {
31 if (cut_ver == PRR_PRODUCT_10) {
32 end_bit = BIT17;
33 } else if (cut_ver == PRR_PRODUCT_11) {
34 end_bit = BIT17;
35 } else {
36 end_bit = BIT20;
37 }
38 } else if ((prr_data & PRR_PRODUCT_MASK) == PRR_PRODUCT_M3) {
39 if (cut_ver == PRR_PRODUCT_10) {
40 end_bit = BIT17;
41 } else {
42 end_bit = BIT20;
43 }
44 } else {
45 end_bit = BIT20;
46 }
47
48 /* SD_INFO */
49 mmc_drv_obj.error_info.info1 = GETR_32(SD_INFO1);
50 mmc_drv_obj.error_info.info2 = GETR_32(SD_INFO2);
51
52 /* SD_INFO EVENT */
53 mmc_drv_obj.int_event1 =
54 mmc_drv_obj.error_info.info1 & GETR_32(SD_INFO1_MASK);
55 mmc_drv_obj.int_event2 =
56 mmc_drv_obj.error_info.info2 & GETR_32(SD_INFO2_MASK);
57
58 /* ERR_STS */
59 mmc_drv_obj.error_info.status1 = GETR_32(SD_ERR_STS1);
60 mmc_drv_obj.error_info.status2 = GETR_32(SD_ERR_STS2);
61
62 /* DM_CM_INFO */
63 mmc_drv_obj.error_info.dm_info1 = GETR_32(DM_CM_INFO1);
64 mmc_drv_obj.error_info.dm_info2 = GETR_32(DM_CM_INFO2);
65
66 /* DM_CM_INFO EVENT */
67 mmc_drv_obj.dm_event1 =
68 mmc_drv_obj.error_info.dm_info1 & GETR_32(DM_CM_INFO1_MASK);
69 mmc_drv_obj.dm_event2 =
70 mmc_drv_obj.error_info.dm_info2 & GETR_32(DM_CM_INFO2_MASK);
71
72 /* ERR SD_INFO2 */
73 if ((SD_INFO2_ALL_ERR & mmc_drv_obj.int_event2) != 0) {
74 SETR_32(SD_INFO1_MASK, 0x00000000U); /* interrupt disable */
75 SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* interrupt disable */
76 SETR_32(SD_INFO1, 0x00000000U); /* interrupt clear */
77 SETR_32(SD_INFO2, SD_INFO2_CLEAR); /* interrupt clear */
78 mmc_drv_obj.state_machine_blocking = FALSE;
79 }
80
81 /* PIO Transfer */
82 /* BWE/BRE */
83 else if (((SD_INFO2_BWE | SD_INFO2_BRE) & mmc_drv_obj.int_event2)) {
84 /* BWE */
85 if (SD_INFO2_BWE & mmc_drv_obj.int_event2) {
86 SETR_32(SD_INFO2, (GETR_32(SD_INFO2) & ~SD_INFO2_BWE));
87 }
88 /* BRE */
89 else {
90 SETR_32(SD_INFO2, (GETR_32(SD_INFO2) & ~SD_INFO2_BRE));
91 }
92
93 result = emmc_trans_sector(mmc_drv_obj.buff_address_virtual);
94 mmc_drv_obj.buff_address_virtual += EMMC_BLOCK_LENGTH;
95 mmc_drv_obj.remain_size -= EMMC_BLOCK_LENGTH;
96
97 if (result != EMMC_SUCCESS) {
98 /* data transfer error */
99 emmc_write_error_info(EMMC_FUNCNO_NONE, result);
100
101 /* Panic */
102 SETR_32(SD_INFO1_MASK, 0x00000000U);
103 SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR);
104 SETR_32(SD_INFO1, 0x00000000U);
105 /* interrupt clear */
106 SETR_32(SD_INFO2, SD_INFO2_CLEAR);
107 mmc_drv_obj.force_terminate = TRUE;
108 } else {
109 mmc_drv_obj.during_transfer = FALSE;
110 }
111 mmc_drv_obj.state_machine_blocking = FALSE;
112 }
113
114 /* DMA_TRANSFER */
115 /* DM_CM_INFO1: DMA-ch0 transfer complete or error occurred */
116 else if ((BIT16 & mmc_drv_obj.dm_event1) != 0) {
117 SETR_32(DM_CM_INFO1, 0x00000000U);
118 SETR_32(DM_CM_INFO2, 0x00000000U);
119 /* interrupt clear */
120 SETR_32(SD_INFO2, (GETR_32(SD_INFO2) & ~SD_INFO2_BWE));
121 /* DM_CM_INFO2: DMA-ch0 error occurred */
122 if ((BIT16 & mmc_drv_obj.dm_event2) != 0) {
123 mmc_drv_obj.dma_error_flag = TRUE;
124 } else {
125 mmc_drv_obj.during_dma_transfer = FALSE;
126 mmc_drv_obj.during_transfer = FALSE;
127 }
128 /* wait next interrupt */
129 mmc_drv_obj.state_machine_blocking = FALSE;
130 }
131 /* DM_CM_INFO1: DMA-ch1 transfer complete or error occurred */
132 else if ((end_bit & mmc_drv_obj.dm_event1) != 0U) {
133 SETR_32(DM_CM_INFO1, 0x00000000U);
134 SETR_32(DM_CM_INFO2, 0x00000000U);
135 /* interrupt clear */
136 SETR_32(SD_INFO2, (GETR_32(SD_INFO2) & ~SD_INFO2_BRE));
137 /* DM_CM_INFO2: DMA-ch1 error occurred */
138 if ((BIT17 & mmc_drv_obj.dm_event2) != 0) {
139 mmc_drv_obj.dma_error_flag = TRUE;
140 } else {
141 mmc_drv_obj.during_dma_transfer = FALSE;
142 mmc_drv_obj.during_transfer = FALSE;
143 }
144 /* wait next interrupt */
145 mmc_drv_obj.state_machine_blocking = FALSE;
146 }
147
148 /* Response end */
149 else if ((SD_INFO1_INFO0 & mmc_drv_obj.int_event1) != 0) {
150 /* interrupt clear */
151 SETR_32(SD_INFO1, (GETR_32(SD_INFO1) & ~SD_INFO1_INFO0));
152 mmc_drv_obj.state_machine_blocking = FALSE;
153 }
154 /* Access end */
155 else if ((SD_INFO1_INFO2 & mmc_drv_obj.int_event1) != 0) {
156 /* interrupt clear */
157 SETR_32(SD_INFO1, (GETR_32(SD_INFO1) & ~SD_INFO1_INFO2));
158 mmc_drv_obj.state_machine_blocking = FALSE;
159 } else {
160 /* nothing to do. */
161 }
162
163 return (uint32_t) 0;
164 }
165
emmc_trans_sector(uint32_t * buff_address_virtual)166 static EMMC_ERROR_CODE emmc_trans_sector(uint32_t *buff_address_virtual)
167 {
168 uint32_t length, i;
169 uint64_t *bufPtrLL;
170
171 if (buff_address_virtual == NULL) {
172 return EMMC_ERR_PARAM;
173 }
174
175 if ((mmc_drv_obj.during_transfer != TRUE)
176 || (mmc_drv_obj.remain_size == 0)) {
177 return EMMC_ERR_STATE;
178 }
179
180 bufPtrLL = (uint64_t *) buff_address_virtual;
181 length = mmc_drv_obj.remain_size;
182
183 /* data transefer */
184 for (i = 0; i < (length >> 3); i++) {
185 /* Write */
186 if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE) {
187 SETR_64(SD_BUF0, *bufPtrLL); /* buffer --> FIFO */
188 }
189 /* Read */
190 else {
191 /* Checks when the read data reaches SD_SIZE. */
192 /* The BRE bit is cleared at emmc_interrupt function. */
193 if (((i %
194 (uint32_t) (EMMC_BLOCK_LENGTH >>
195 EMMC_BUF_SIZE_SHIFT)) == 0U)
196 && (i != 0U)) {
197 /* BRE check */
198 while (((GETR_32(SD_INFO2)) & SD_INFO2_BRE) ==
199 0U) {
200 /* ERROR check */
201 if (((GETR_32(SD_INFO2)) &
202 SD_INFO2_ALL_ERR) != 0U) {
203 return EMMC_ERR_TRANSFER;
204 }
205 }
206 /* BRE clear */
207 SETR_32(SD_INFO2,
208 (uint32_t) (GETR_32(SD_INFO2) &
209 ~SD_INFO2_BRE));
210 }
211 *bufPtrLL = GETR_64(SD_BUF0); /* FIFO --> buffer */
212 }
213 bufPtrLL++;
214 }
215
216 return EMMC_SUCCESS;
217 }
218