1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef GIC_COMMON_H 8 #define GIC_COMMON_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * GIC Distributor interface general definitions 14 ******************************************************************************/ 15 /* Constants to categorise interrupts */ 16 #define MIN_SGI_ID U(0) 17 #define MIN_SEC_SGI_ID U(8) 18 #define MIN_PPI_ID U(16) 19 #define MIN_SPI_ID U(32) 20 #define MAX_SPI_ID U(1019) 21 22 #define TOTAL_SPI_INTR_NUM (MAX_SPI_ID - MIN_SPI_ID + U(1)) 23 #define TOTAL_PCPU_INTR_NUM (MIN_SPI_ID - MIN_SGI_ID) 24 25 /* Mask for the priority field common to all GIC interfaces */ 26 #define GIC_PRI_MASK U(0xff) 27 28 /* Mask for the configuration field common to all GIC interfaces */ 29 #define GIC_CFG_MASK U(0x3) 30 31 /* Constant to indicate a spurious interrupt in all GIC versions */ 32 #define GIC_SPURIOUS_INTERRUPT U(1023) 33 34 /* Interrupt configurations: 2-bit fields with LSB reserved */ 35 #define GIC_INTR_CFG_LEVEL (0 << 1) 36 #define GIC_INTR_CFG_EDGE (1 << 1) 37 38 /* Highest possible interrupt priorities */ 39 #define GIC_HIGHEST_SEC_PRIORITY U(0x00) 40 #define GIC_HIGHEST_NS_PRIORITY U(0x80) 41 42 /******************************************************************************* 43 * Common GIC Distributor interface register offsets 44 ******************************************************************************/ 45 #define GICD_CTLR U(0x0) 46 #define GICD_TYPER U(0x4) 47 #define GICD_IIDR U(0x8) 48 #define GICD_IGROUPR U(0x80) 49 #define GICD_ISENABLER U(0x100) 50 #define GICD_ICENABLER U(0x180) 51 #define GICD_ISPENDR U(0x200) 52 #define GICD_ICPENDR U(0x280) 53 #define GICD_ISACTIVER U(0x300) 54 #define GICD_ICACTIVER U(0x380) 55 #define GICD_IPRIORITYR U(0x400) 56 #define GICD_ICFGR U(0xc00) 57 #define GICD_NSACR U(0xe00) 58 59 /* GICD_CTLR bit definitions */ 60 #define CTLR_ENABLE_G0_SHIFT 0 61 #define CTLR_ENABLE_G0_MASK U(0x1) 62 #define CTLR_ENABLE_G0_BIT BIT_32(CTLR_ENABLE_G0_SHIFT) 63 64 /******************************************************************************* 65 * Common GIC Distributor interface register constants 66 ******************************************************************************/ 67 #define PIDR2_ARCH_REV_SHIFT 4 68 #define PIDR2_ARCH_REV_MASK U(0xf) 69 70 /* GIC revision as reported by PIDR2.ArchRev register field */ 71 #define ARCH_REV_GICV1 U(0x1) 72 #define ARCH_REV_GICV2 U(0x2) 73 #define ARCH_REV_GICV3 U(0x3) 74 #define ARCH_REV_GICV4 U(0x4) 75 76 #define IGROUPR_SHIFT 5 77 #define ISENABLER_SHIFT 5 78 #define ICENABLER_SHIFT ISENABLER_SHIFT 79 #define ISPENDR_SHIFT 5 80 #define ICPENDR_SHIFT ISPENDR_SHIFT 81 #define ISACTIVER_SHIFT 5 82 #define ICACTIVER_SHIFT ISACTIVER_SHIFT 83 #define IPRIORITYR_SHIFT 2 84 #define ITARGETSR_SHIFT 2 85 #define ICFGR_SHIFT 4 86 #define NSACR_SHIFT 4 87 88 /* GICD_TYPER shifts and masks */ 89 #define TYPER_IT_LINES_NO_SHIFT U(0) 90 #define TYPER_IT_LINES_NO_MASK U(0x1f) 91 92 /* Value used to initialize Normal world interrupt priorities four at a time */ 93 #define GICD_IPRIORITYR_DEF_VAL \ 94 (GIC_HIGHEST_NS_PRIORITY | \ 95 (GIC_HIGHEST_NS_PRIORITY << 8) | \ 96 (GIC_HIGHEST_NS_PRIORITY << 16) | \ 97 (GIC_HIGHEST_NS_PRIORITY << 24)) 98 99 #endif /* GIC_COMMON_H */ 100