1 /* Copyright (c) 2002 Intel Corporation */
2 #include <stdio.h>
3 #include "internal.h"
4
5 /* Register Bit Masks */
6 /* Device Control */
7 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
8 #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
9 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
10 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
11 #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
12 #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
13 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
14 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
15 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
16 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
17 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
18 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
19 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
20 #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
21 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
22 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
23 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
24 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
25 #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
26 #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
27 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
28 #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
29 #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
30 #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
31 #define E1000_CTRL_RST 0x04000000 /* Global reset */
32 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
33 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
34 #define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
35 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
36 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
37
38 /* Device Status */
39 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
40 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
41 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
42 #define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
43 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
44 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
45 #define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
46 #define E1000_STATUS_SPEED_MASK 0x000000C0
47 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
48 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
49 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
50 #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
51 #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
52 #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
53 #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
54 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
55 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
56
57 /* Constants used to intrepret the masked PCI-X bus speed. */
58 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
59 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
60 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
61
62 /* Receive Control */
63 #define E1000_RCTL_RST 0x00000001 /* Software reset */
64 #define E1000_RCTL_EN 0x00000002 /* enable */
65 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */
66 #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
67 #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
68 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */
69 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
70 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
71 #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
72 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
73 #define E1000_RCTL_RDMTS 0x00000300 /* rx desc min threshold size */
74 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
75 #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
76 #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
77 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
78 #define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
79 #define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
80 #define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
81 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
82 #define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
83 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
84 #define E1000_RCTL_SZ 0x00030000 /* rx buffer size */
85 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
86 #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
87 #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
88 #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
89 #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
90 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
91 #define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
92 #define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
93 #define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
94 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
95 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
96 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
97 #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
98 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
99 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
100
101 /* Transmit Control */
102 #define E1000_TCTL_RST 0x00000001 /* software reset */
103 #define E1000_TCTL_EN 0x00000002 /* enable tx */
104 #define E1000_TCTL_BCE 0x00000004 /* busy check enable */
105 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */
106 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
107 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */
108 #define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
109 #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
110 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
111 #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
112
113 /* M88E1000 PHY Specific Status Register */
114 #define M88_PSSR_JABBER 0x0001 /* 1=Jabber */
115 #define M88_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
116 #define M88_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
117 #define M88_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
118 #define M88_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
119 * 3=110-140M;4=>140M */
120 #define M88_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
121 #define M88_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
122 #define M88_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
123 #define M88_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
124 #define M88_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
125 #define M88_PSSR_10MBS 0x0000 /* 00=10Mbs */
126 #define M88_PSSR_100MBS 0x4000 /* 01=100Mbs */
127 #define M88_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
128
129 #define M88_PSSR_CL_0_50 (0<<7)
130 #define M88_PSSR_CL_50_80 (1<<7)
131 #define M88_PSSR_CL_80_110 (2<<7)
132 #define M88_PSSR_CL_110_140 (3<<7)
133 #define M88_PSSR_CL_140_PLUS (4<<7)
134
135 /* M88E1000 PHY Specific Control Register */
136 #define M88_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
137 #define M88_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
138 #define M88_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
139 #define M88_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
140 * 0=CLK125 toggling
141 */
142 #define M88_PSCR_MDI_MASK 0x0060
143 #define M88_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
144 /* Manual MDI configuration */
145 #define M88_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
146 #define M88_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
147 * 100BASE-TX/10BASE-T:
148 * MDI Mode
149 */
150 #define M88_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
151 * all speeds.
152 */
153 #define M88_PSCR_10BT_EXT_DIST_ENABLE 0x0080
154 /* 1=Enable Extended 10BASE-T distance
155 * (Lower 10BASE-T RX Threshold)
156 * 0=Normal 10BASE-T RX Threshold */
157 #define M88_PSCR_MII_5BIT_ENABLE 0x0100
158 /* 1=5-Bit interface in 100BASE-TX
159 * 0=MII interface in 100BASE-TX */
160 #define M88_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
161 #define M88_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
162 #define M88_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
163
164 #define M88_PSCR_POLARITY_REVERSAL_SHIFT 1
165 #define M88_PSCR_AUTO_X_MODE_SHIFT 5
166 #define M88_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
167
168 /* PCI Device IDs */
169 #define E1000_DEV_ID_82542 0x1000
170 #define E1000_DEV_ID_82543GC_FIBER 0x1001
171 #define E1000_DEV_ID_82543GC_COPPER 0x1004
172 #define E1000_DEV_ID_82544EI_COPPER 0x1008
173 #define E1000_DEV_ID_82544EI_FIBER 0x1009
174 #define E1000_DEV_ID_82544GC_COPPER 0x100C
175 #define E1000_DEV_ID_82544GC_LOM 0x100D
176 #define E1000_DEV_ID_82540EM 0x100E
177 #define E1000_DEV_ID_82540EM_LOM 0x1015
178 #define E1000_DEV_ID_82540EP_LOM 0x1016
179 #define E1000_DEV_ID_82540EP 0x1017
180 #define E1000_DEV_ID_82540EP_LP 0x101E
181 #define E1000_DEV_ID_82545EM_COPPER 0x100F
182 #define E1000_DEV_ID_82545EM_FIBER 0x1011
183 #define E1000_DEV_ID_82545GM_COPPER 0x1026
184 #define E1000_DEV_ID_82545GM_FIBER 0x1027
185 #define E1000_DEV_ID_82545GM_SERDES 0x1028
186 #define E1000_DEV_ID_82546EB_COPPER 0x1010
187 #define E1000_DEV_ID_82546EB_FIBER 0x1012
188 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
189 #define E1000_DEV_ID_82546GB_COPPER 0x1079
190 #define E1000_DEV_ID_82546GB_FIBER 0x107A
191 #define E1000_DEV_ID_82546GB_SERDES 0x107B
192 #define E1000_DEV_ID_82546GB_PCIE 0x108A
193 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
194 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
195 #define E1000_DEV_ID_82541EI 0x1013
196 #define E1000_DEV_ID_82541EI_MOBILE 0x1018
197 #define E1000_DEV_ID_82541ER_LOM 0x1014
198 #define E1000_DEV_ID_82541ER 0x1078
199 #define E1000_DEV_ID_82541GI 0x1076
200 #define E1000_DEV_ID_82541GI_LF 0x107C
201 #define E1000_DEV_ID_82541GI_MOBILE 0x1077
202 #define E1000_DEV_ID_82547EI 0x1019
203 #define E1000_DEV_ID_82547EI_MOBILE 0x101A
204 #define E1000_DEV_ID_82547GI 0x1075
205 #define E1000_DEV_ID_82571EB_COPPER 0x105E
206 #define E1000_DEV_ID_82571EB_FIBER 0x105F
207 #define E1000_DEV_ID_82571EB_SERDES 0x1060
208 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
209 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
210 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
211 #define E1000_DEV_ID_82572EI_COPPER 0x107D
212 #define E1000_DEV_ID_82572EI_FIBER 0x107E
213 #define E1000_DEV_ID_82572EI_SERDES 0x107F
214 #define E1000_DEV_ID_82572EI 0x10B9
215 #define E1000_DEV_ID_82573E 0x108B
216 #define E1000_DEV_ID_82573E_IAMT 0x108C
217 #define E1000_DEV_ID_82573L 0x109A
218 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
219 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
220 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
221 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
222 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
223 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
224 #define E1000_DEV_ID_ICH8_IGP_C 0x104B
225 #define E1000_DEV_ID_ICH8_IFE 0x104C
226 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
227 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5
228 #define E1000_DEV_ID_ICH8_IGP_M 0x104D
229
230 #define E1000_82542_2_0_REV_ID 2
231 #define E1000_82542_2_1_REV_ID 3
232
233 /* Enumerated types specific to the e1000 hardware */
234 /* Media Access Controlers */
235 enum e1000_mac_type {
236 e1000_undefined = 0,
237 e1000_82542,
238 e1000_82543,
239 e1000_82544,
240 e1000_82540,
241 e1000_82545,
242 e1000_82545_rev_3,
243 e1000_82546,
244 e1000_82546_rev_3,
245 e1000_82541,
246 e1000_82541_rev_2,
247 e1000_82547,
248 e1000_82547_rev_2,
249 e1000_82571,
250 e1000_82572,
251 e1000_82573,
252 e1000_80003es2lan,
253 e1000_ich8lan,
254 e1000_num_macs
255 };
256
e1000_get_mac_type(u16 device_id)257 static enum e1000_mac_type e1000_get_mac_type(u16 device_id)
258 {
259 enum e1000_mac_type mac_type = e1000_undefined;
260
261 switch (device_id) {
262 case E1000_DEV_ID_82542:
263 mac_type = e1000_82542;
264 break;
265 case E1000_DEV_ID_82543GC_FIBER:
266 case E1000_DEV_ID_82543GC_COPPER:
267 mac_type = e1000_82543;
268 break;
269 case E1000_DEV_ID_82544EI_COPPER:
270 case E1000_DEV_ID_82544EI_FIBER:
271 case E1000_DEV_ID_82544GC_COPPER:
272 case E1000_DEV_ID_82544GC_LOM:
273 mac_type = e1000_82544;
274 break;
275 case E1000_DEV_ID_82540EM:
276 case E1000_DEV_ID_82540EM_LOM:
277 case E1000_DEV_ID_82540EP:
278 case E1000_DEV_ID_82540EP_LOM:
279 case E1000_DEV_ID_82540EP_LP:
280 mac_type = e1000_82540;
281 break;
282 case E1000_DEV_ID_82545EM_COPPER:
283 case E1000_DEV_ID_82545EM_FIBER:
284 mac_type = e1000_82545;
285 break;
286 case E1000_DEV_ID_82545GM_COPPER:
287 case E1000_DEV_ID_82545GM_FIBER:
288 case E1000_DEV_ID_82545GM_SERDES:
289 mac_type = e1000_82545_rev_3;
290 break;
291 case E1000_DEV_ID_82546EB_COPPER:
292 case E1000_DEV_ID_82546EB_FIBER:
293 case E1000_DEV_ID_82546EB_QUAD_COPPER:
294 mac_type = e1000_82546;
295 break;
296 case E1000_DEV_ID_82546GB_COPPER:
297 case E1000_DEV_ID_82546GB_FIBER:
298 case E1000_DEV_ID_82546GB_SERDES:
299 case E1000_DEV_ID_82546GB_PCIE:
300 case E1000_DEV_ID_82546GB_QUAD_COPPER:
301 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
302 mac_type = e1000_82546_rev_3;
303 break;
304 case E1000_DEV_ID_82541EI:
305 case E1000_DEV_ID_82541EI_MOBILE:
306 case E1000_DEV_ID_82541ER_LOM:
307 mac_type = e1000_82541;
308 break;
309 case E1000_DEV_ID_82541ER:
310 case E1000_DEV_ID_82541GI:
311 case E1000_DEV_ID_82541GI_LF:
312 case E1000_DEV_ID_82541GI_MOBILE:
313 mac_type = e1000_82541_rev_2;
314 break;
315 case E1000_DEV_ID_82547EI:
316 case E1000_DEV_ID_82547EI_MOBILE:
317 mac_type = e1000_82547;
318 break;
319 case E1000_DEV_ID_82547GI:
320 mac_type = e1000_82547_rev_2;
321 break;
322 case E1000_DEV_ID_82571EB_COPPER:
323 case E1000_DEV_ID_82571EB_FIBER:
324 case E1000_DEV_ID_82571EB_SERDES:
325 case E1000_DEV_ID_82571EB_QUAD_COPPER:
326 case E1000_DEV_ID_82571EB_QUAD_FIBER:
327 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
328 mac_type = e1000_82571;
329 break;
330 case E1000_DEV_ID_82572EI:
331 case E1000_DEV_ID_82572EI_COPPER:
332 case E1000_DEV_ID_82572EI_FIBER:
333 case E1000_DEV_ID_82572EI_SERDES:
334 mac_type = e1000_82572;
335 break;
336 case E1000_DEV_ID_82573E:
337 case E1000_DEV_ID_82573E_IAMT:
338 case E1000_DEV_ID_82573L:
339 mac_type = e1000_82573;
340 break;
341 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
342 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
343 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
344 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
345 mac_type = e1000_80003es2lan;
346 break;
347 case E1000_DEV_ID_ICH8_IFE:
348 case E1000_DEV_ID_ICH8_IFE_GT:
349 case E1000_DEV_ID_ICH8_IFE_G:
350 case E1000_DEV_ID_ICH8_IGP_M:
351 case E1000_DEV_ID_ICH8_IGP_M_AMT:
352 case E1000_DEV_ID_ICH8_IGP_AMT:
353 case E1000_DEV_ID_ICH8_IGP_C:
354 mac_type = e1000_ich8lan;
355 break;
356 default:
357 /* assume old nic and attempt so user can get limited
358 * functionality */
359 mac_type = e1000_82543;
360 break;
361 }
362
363 return mac_type;
364 }
365
e1000_dump_regs(struct ethtool_drvinfo * info maybe_unused,struct ethtool_regs * regs)366 int e1000_dump_regs(struct ethtool_drvinfo *info maybe_unused,
367 struct ethtool_regs *regs)
368 {
369 u32 *regs_buff = (u32 *)regs->data;
370 u16 hw_device_id = (u16)regs->version;
371 /* u8 hw_revision_id = (u8)(regs->version >> 16); */
372 u8 version = (u8)(regs->version >> 24);
373 enum e1000_mac_type mac_type;
374 u32 reg;
375
376 if (version != 1)
377 return -1;
378
379 mac_type = e1000_get_mac_type(hw_device_id);
380
381 if(mac_type == e1000_undefined)
382 return -1;
383
384 fprintf(stdout, "MAC Registers\n");
385 fprintf(stdout, "-------------\n");
386
387 /* Device control register */
388 reg = regs_buff[0];
389 fprintf(stdout,
390 "0x00000: CTRL (Device control register) 0x%08X\n"
391 " Endian mode (buffers): %s\n"
392 " Link reset: %s\n"
393 " Set link up: %s\n"
394 " Invert Loss-Of-Signal: %s\n"
395 " Receive flow control: %s\n"
396 " Transmit flow control: %s\n"
397 " VLAN mode: %s\n",
398 reg,
399 reg & E1000_CTRL_BEM ? "big" : "little",
400 reg & E1000_CTRL_LRST ? "reset" : "normal",
401 reg & E1000_CTRL_SLU ? "1" : "0",
402 reg & E1000_CTRL_ILOS ? "yes" : "no",
403 reg & E1000_CTRL_RFCE ? "enabled" : "disabled",
404 reg & E1000_CTRL_TFCE ? "enabled" : "disabled",
405 reg & E1000_CTRL_VME ? "enabled" : "disabled");
406 if(mac_type >= e1000_82543) {
407 fprintf(stdout,
408 " Auto speed detect: %s\n"
409 " Speed select: %s\n"
410 " Force speed: %s\n"
411 " Force duplex: %s\n",
412 reg & E1000_CTRL_ASDE ? "enabled" : "disabled",
413 (reg & E1000_CTRL_SPD_SEL) == E1000_CTRL_SPD_10 ? "10Mb/s" :
414 (reg & E1000_CTRL_SPD_SEL) == E1000_CTRL_SPD_100 ? "100Mb/s" :
415 (reg & E1000_CTRL_SPD_SEL) == E1000_CTRL_SPD_1000 ? "1000Mb/s" :
416 "not used",
417 reg & E1000_CTRL_FRCSPD ? "yes" : "no",
418 reg & E1000_CTRL_FRCDPX ? "yes" : "no");
419 }
420
421 /* Device status register */
422 reg = regs_buff[1];
423 fprintf(stdout,
424 "0x00008: STATUS (Device status register) 0x%08X\n"
425 " Duplex: %s\n"
426 " Link up: %s\n",
427 reg,
428 reg & E1000_STATUS_FD ? "full" : "half",
429 reg & E1000_STATUS_LU ? "link config" : "no link config");
430 if (mac_type >= e1000_82571) {
431 fprintf(stdout,
432 " TBI mode: %s\n"
433 " Link speed: %s\n"
434 " Bus type: %s\n"
435 " Port number: %s\n",
436 reg & E1000_STATUS_TBIMODE ? "enabled" : "disabled",
437 (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_10 ?
438 "10Mb/s" :
439 (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_100 ?
440 "100Mb/s" :
441 (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_1000 ?
442 "1000Mb/s" : "not used",
443 "PCI Express",
444 (reg & E1000_STATUS_FUNC_MASK) == 0 ? "0" : "1");
445 }
446 else if (mac_type >= e1000_82543) {
447 fprintf(stdout,
448 " TBI mode: %s\n"
449 " Link speed: %s\n"
450 " Bus type: %s\n"
451 " Bus speed: %s\n"
452 " Bus width: %s\n",
453 reg & E1000_STATUS_TBIMODE ? "enabled" : "disabled",
454 (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_10 ?
455 "10Mb/s" :
456 (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_100 ?
457 "100Mb/s" :
458 (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_1000 ?
459 "1000Mb/s" : "not used",
460 (reg & E1000_STATUS_PCIX_MODE) ? "PCI-X" : "PCI",
461 (reg & E1000_STATUS_PCIX_MODE) ?
462 ((reg & E1000_STATUS_PCIX_SPEED_133) ? "133MHz" :
463 (reg & E1000_STATUS_PCIX_SPEED_100) ? "100MHz" :
464 "66MHz") :
465 ((reg & E1000_STATUS_PCI66) ? "66MHz" : "33MHz"),
466 (reg & E1000_STATUS_BUS64) ? "64-bit" : "32-bit");
467 }
468
469 /* Receive control register */
470 reg = regs_buff[2];
471 fprintf(stdout,
472 "0x00100: RCTL (Receive control register) 0x%08X\n"
473 " Receiver: %s\n"
474 " Store bad packets: %s\n"
475 " Unicast promiscuous: %s\n"
476 " Multicast promiscuous: %s\n"
477 " Long packet: %s\n"
478 " Descriptor minimum threshold size: %s\n"
479 " Broadcast accept mode: %s\n"
480 " VLAN filter: %s\n"
481 " Canonical form indicator: %s\n"
482 " Discard pause frames: %s\n"
483 " Pass MAC control frames: %s\n",
484 reg,
485 reg & E1000_RCTL_EN ? "enabled" : "disabled",
486 reg & E1000_RCTL_SBP ? "enabled" : "disabled",
487 reg & E1000_RCTL_UPE ? "enabled" : "disabled",
488 reg & E1000_RCTL_MPE ? "enabled" : "disabled",
489 reg & E1000_RCTL_LPE ? "enabled" : "disabled",
490 (reg & E1000_RCTL_RDMTS) == E1000_RCTL_RDMTS_HALF ? "1/2" :
491 (reg & E1000_RCTL_RDMTS) == E1000_RCTL_RDMTS_QUAT ? "1/4" :
492 (reg & E1000_RCTL_RDMTS) == E1000_RCTL_RDMTS_EIGTH ? "1/8" :
493 "reserved",
494 reg & E1000_RCTL_BAM ? "accept" : "ignore",
495 reg & E1000_RCTL_VFE ? "enabled" : "disabled",
496 reg & E1000_RCTL_CFIEN ? "enabled" : "disabled",
497 reg & E1000_RCTL_DPF ? "ignored" : "filtered",
498 reg & E1000_RCTL_PMCF ? "pass" : "don't pass");
499 if(mac_type >= e1000_82543) {
500 fprintf(stdout,
501 " Receive buffer size: %s\n",
502 reg & E1000_RCTL_BSEX ?
503 ((reg & E1000_RCTL_SZ)==E1000_RCTL_SZ_16384 ? "16384" :
504 (reg & E1000_RCTL_SZ)==E1000_RCTL_SZ_8192 ? "8192" :
505 (reg & E1000_RCTL_SZ)==E1000_RCTL_SZ_4096 ? "4096" :
506 "reserved") :
507 ((reg & E1000_RCTL_SZ)==E1000_RCTL_SZ_2048 ? "2048" :
508 (reg & E1000_RCTL_SZ)==E1000_RCTL_SZ_1024 ? "1024" :
509 (reg & E1000_RCTL_SZ)==E1000_RCTL_SZ_512 ? "512" :
510 "256"));
511 } else {
512 fprintf(stdout,
513 " Receive buffer size: %s\n",
514 (reg & E1000_RCTL_SZ) == E1000_RCTL_SZ_2048 ? "2048" :
515 (reg & E1000_RCTL_SZ) == E1000_RCTL_SZ_1024 ? "1024" :
516 (reg & E1000_RCTL_SZ) == E1000_RCTL_SZ_512 ? "512" :
517 "256");
518 }
519
520 /* Receive descriptor registers */
521 fprintf(stdout,
522 "0x02808: RDLEN (Receive desc length) 0x%08X\n",
523 regs_buff[3]);
524 fprintf(stdout,
525 "0x02810: RDH (Receive desc head) 0x%08X\n",
526 regs_buff[4]);
527 fprintf(stdout,
528 "0x02818: RDT (Receive desc tail) 0x%08X\n",
529 regs_buff[5]);
530 fprintf(stdout,
531 "0x02820: RDTR (Receive delay timer) 0x%08X\n",
532 regs_buff[6]);
533
534 /* Transmit control register */
535 reg = regs_buff[7];
536 fprintf(stdout,
537 "0x00400: TCTL (Transmit ctrl register) 0x%08X\n"
538 " Transmitter: %s\n"
539 " Pad short packets: %s\n"
540 " Software XOFF Transmission: %s\n",
541 reg,
542 reg & E1000_TCTL_EN ? "enabled" : "disabled",
543 reg & E1000_TCTL_PSP ? "enabled" : "disabled",
544 reg & E1000_TCTL_SWXOFF ? "enabled" : "disabled");
545 if(mac_type >= e1000_82543) {
546 fprintf(stdout,
547 " Re-transmit on late collision: %s\n",
548 reg & E1000_TCTL_RTLC ? "enabled" : "disabled");
549 }
550
551 /* Transmit descriptor registers */
552 fprintf(stdout,
553 "0x03808: TDLEN (Transmit desc length) 0x%08X\n",
554 regs_buff[8]);
555 fprintf(stdout,
556 "0x03810: TDH (Transmit desc head) 0x%08X\n",
557 regs_buff[9]);
558 fprintf(stdout,
559 "0x03818: TDT (Transmit desc tail) 0x%08X\n",
560 regs_buff[10]);
561 fprintf(stdout,
562 "0x03820: TIDV (Transmit delay timer) 0x%08X\n",
563 regs_buff[11]);
564
565 /* PHY type */
566 fprintf(stdout,
567 "PHY type: %s\n",
568 regs_buff[12] == 0 ? "M88" :
569 regs_buff[12] == 1 ? "IGP" :
570 regs_buff[12] == 2 ? "IGP2" : "unknown" );
571
572 if (0 == regs_buff[12]) {
573 reg = regs_buff[13];
574 fprintf(stdout,
575 "M88 PHY STATUS REGISTER: 0x%08X\n"
576 " Jabber: %s\n"
577 " Polarity: %s\n"
578 " Downshifted: %s\n"
579 " MDI/MDIX: %s\n"
580 " Cable Length Estimate: %s meters\n"
581 " Link State: %s\n"
582 " Speed & Duplex Resolved: %s\n"
583 " Page Received: %s\n"
584 " Duplex: %s\n"
585 " Speed: %s mbps\n",
586 reg,
587 reg & M88_PSSR_JABBER ? "yes" : "no",
588 reg & M88_PSSR_REV_POLARITY ? "reverse" : "normal",
589 reg & M88_PSSR_DOWNSHIFT ? "yes" : "no",
590 reg & M88_PSSR_MDIX ? "MDIX" : "MDI",
591 ((reg & M88_PSSR_CABLE_LENGTH)==M88_PSSR_CL_0_50 ? "0-50"
592 : (reg & M88_PSSR_CABLE_LENGTH)==M88_PSSR_CL_50_80 ? "50-80"
593 : (reg & M88_PSSR_CABLE_LENGTH)==M88_PSSR_CL_80_110 ? "80-110"
594 : (reg & M88_PSSR_CABLE_LENGTH)==M88_PSSR_CL_110_140? "110-140"
595 : (reg & M88_PSSR_CABLE_LENGTH)==M88_PSSR_CL_140_PLUS ? "140+"
596 : "unknown"),
597 reg & M88_PSSR_LINK ? "Up" : "Down",
598 reg & M88_PSSR_SPD_DPLX_RESOLVED ? "Yes" : "No",
599 reg & M88_PSSR_PAGE_RCVD ? "Yes" : "No",
600 reg & M88_PSSR_DPLX ? "Full" : "Half",
601 ((reg & M88_PSSR_SPEED)==M88_PSSR_10MBS ? "10"
602 : (reg & M88_PSSR_SPEED)==M88_PSSR_100MBS ? "100"
603 : (reg & M88_PSSR_SPEED)==M88_PSSR_1000MBS ? "1000"
604 : "unknown")
605 );
606
607 reg = regs_buff[17];
608 fprintf(stdout,
609 "M88 PHY CONTROL REGISTER: 0x%08X\n"
610 " Jabber function: %s\n"
611 " Auto-polarity: %s\n"
612 " SQE Test: %s\n"
613 " CLK125: %s\n"
614 " Auto-MDIX: %s\n"
615 " Extended 10Base-T Distance: %s\n"
616 " 100Base-TX Interface: %s\n"
617 " Scrambler: %s\n"
618 " Force Link Good: %s\n"
619 " Assert CRS on Transmit: %s\n",
620 reg,
621 reg & M88_PSCR_JABBER_DISABLE ? "disabled" : "enabled",
622 reg & M88_PSCR_POLARITY_REVERSAL ? "enabled" : "disabled",
623 reg & M88_PSCR_SQE_TEST ? "enabled" : "disabled",
624 reg & M88_PSCR_CLK125_DISABLE ? "disabled" : "enabled",
625 ((reg & M88_PSCR_MDI_MASK)==M88_PSCR_MDI_MANUAL_MODE ? "force MDI"
626 : (reg & M88_PSCR_MDI_MASK)==M88_PSCR_MDIX_MANUAL_MODE ? "force MDIX"
627 : (reg & M88_PSCR_MDI_MASK)==M88_PSCR_AUTO_X_1000T ? "1000 auto, 10/100 MDI"
628 : (reg & M88_PSCR_MDI_MASK)==M88_PSCR_AUTO_X_MODE ? "auto"
629 : "wtf"),
630 reg & M88_PSCR_10BT_EXT_DIST_ENABLE ? "enabled" : "disabled",
631 reg & M88_PSCR_MII_5BIT_ENABLE ? "5-bit" : "MII",
632 reg & M88_PSCR_SCRAMBLER_DISABLE ? "disabled" : "enabled",
633 reg & M88_PSCR_FORCE_LINK_GOOD ? "forced" : "disabled",
634 reg & M88_PSCR_ASSERT_CRS_ON_TX ? "enabled" : "disabled"
635 );
636 }
637
638 return 0;
639 }
640
641