1 //===- llvm/CodeGen/GlobalISel/InstructionSelector.cpp --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file implements the InstructionSelector class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
15 #include "llvm/CodeGen/GlobalISel/Utils.h"
16 #include "llvm/CodeGen/MachineBasicBlock.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstr.h"
19 #include "llvm/CodeGen/MachineOperand.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/TargetRegisterInfo.h"
22 #include "llvm/MC/MCInstrDesc.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/raw_ostream.h"
25 #include <cassert>
26
27 #define DEBUG_TYPE "instructionselector"
28
29 using namespace llvm;
30
MatcherState(unsigned MaxRenderers)31 InstructionSelector::MatcherState::MatcherState(unsigned MaxRenderers)
32 : Renderers(MaxRenderers), MIs() {}
33
34 InstructionSelector::InstructionSelector() = default;
35
constrainOperandRegToRegClass(MachineInstr & I,unsigned OpIdx,const TargetRegisterClass & RC,const TargetInstrInfo & TII,const TargetRegisterInfo & TRI,const RegisterBankInfo & RBI) const36 bool InstructionSelector::constrainOperandRegToRegClass(
37 MachineInstr &I, unsigned OpIdx, const TargetRegisterClass &RC,
38 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI,
39 const RegisterBankInfo &RBI) const {
40 MachineBasicBlock &MBB = *I.getParent();
41 MachineFunction &MF = *MBB.getParent();
42 MachineRegisterInfo &MRI = MF.getRegInfo();
43
44 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, RC,
45 I.getOperand(OpIdx));
46 }
47
isOperandImmEqual(const MachineOperand & MO,int64_t Value,const MachineRegisterInfo & MRI) const48 bool InstructionSelector::isOperandImmEqual(
49 const MachineOperand &MO, int64_t Value,
50 const MachineRegisterInfo &MRI) const {
51 if (MO.isReg() && MO.getReg())
52 if (auto VRegVal = getConstantVRegValWithLookThrough(MO.getReg(), MRI))
53 return VRegVal->Value == Value;
54 return false;
55 }
56
isBaseWithConstantOffset(const MachineOperand & Root,const MachineRegisterInfo & MRI) const57 bool InstructionSelector::isBaseWithConstantOffset(
58 const MachineOperand &Root, const MachineRegisterInfo &MRI) const {
59 if (!Root.isReg())
60 return false;
61
62 MachineInstr *RootI = MRI.getVRegDef(Root.getReg());
63 if (RootI->getOpcode() != TargetOpcode::G_PTR_ADD)
64 return false;
65
66 MachineOperand &RHS = RootI->getOperand(2);
67 MachineInstr *RHSI = MRI.getVRegDef(RHS.getReg());
68 if (RHSI->getOpcode() != TargetOpcode::G_CONSTANT)
69 return false;
70
71 return true;
72 }
73
isObviouslySafeToFold(MachineInstr & MI,MachineInstr & IntoMI) const74 bool InstructionSelector::isObviouslySafeToFold(MachineInstr &MI,
75 MachineInstr &IntoMI) const {
76 // Immediate neighbours are already folded.
77 if (MI.getParent() == IntoMI.getParent() &&
78 std::next(MI.getIterator()) == IntoMI.getIterator())
79 return true;
80
81 return !MI.mayLoadOrStore() && !MI.mayRaiseFPException() &&
82 !MI.hasUnmodeledSideEffects() && MI.implicit_operands().empty();
83 }
84