1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// SI DAG Lowering interface definition 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 15 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 16 17 #include "AMDGPUISelLowering.h" 18 #include "AMDGPUArgumentUsageInfo.h" 19 #include "SIInstrInfo.h" 20 21 namespace llvm { 22 23 class SITargetLowering final : public AMDGPUTargetLowering { 24 private: 25 const GCNSubtarget *Subtarget; 26 27 public: 28 MVT getRegisterTypeForCallingConv(LLVMContext &Context, 29 CallingConv::ID CC, 30 EVT VT) const override; 31 unsigned getNumRegistersForCallingConv(LLVMContext &Context, 32 CallingConv::ID CC, 33 EVT VT) const override; 34 35 unsigned getVectorTypeBreakdownForCallingConv( 36 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, 37 unsigned &NumIntermediates, MVT &RegisterVT) const override; 38 39 private: 40 SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL, 41 SDValue Chain, uint64_t Offset) const; 42 SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const; 43 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, 44 const SDLoc &SL, SDValue Chain, 45 uint64_t Offset, Align Alignment, 46 bool Signed, 47 const ISD::InputArg *Arg = nullptr) const; 48 49 SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA, 50 const SDLoc &SL, SDValue Chain, 51 const ISD::InputArg &Arg) const; 52 SDValue getPreloadedValue(SelectionDAG &DAG, 53 const SIMachineFunctionInfo &MFI, 54 EVT VT, 55 AMDGPUFunctionArgInfo::PreloadedValue) const; 56 57 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, 58 SelectionDAG &DAG) const override; 59 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op, 60 MVT VT, unsigned Offset) const; 61 SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr, 62 SelectionDAG &DAG, bool WithChain) const; 63 SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset, 64 SDValue CachePolicy, SelectionDAG &DAG) const; 65 66 SDValue lowerRawBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG, 67 unsigned NewOpcode) const; 68 SDValue lowerStructBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG, 69 unsigned NewOpcode) const; 70 71 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 72 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 73 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 74 75 // The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset 76 // (the offset that is included in bounds checking and swizzling, to be split 77 // between the instruction's voffset and immoffset fields) and soffset (the 78 // offset that is excluded from bounds checking and swizzling, to go in the 79 // instruction's soffset field). This function takes the first kind of 80 // offset and figures out how to split it between voffset and immoffset. 81 std::pair<SDValue, SDValue> splitBufferOffsets(SDValue Offset, 82 SelectionDAG &DAG) const; 83 84 SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const; 85 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 86 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 87 SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const; 88 SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const; 89 SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const; 90 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const; 91 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const; 92 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const; 93 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 94 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const; 95 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 96 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 97 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 98 SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M, 99 SelectionDAG &DAG, ArrayRef<SDValue> Ops, 100 bool IsIntrinsic = false) const; 101 102 SDValue lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, SelectionDAG &DAG, 103 ArrayRef<SDValue> Ops) const; 104 105 // Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to 106 // dwordx4 if on SI. 107 SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, 108 ArrayRef<SDValue> Ops, EVT MemVT, 109 MachineMemOperand *MMO, SelectionDAG &DAG) const; 110 111 SDValue handleD16VData(SDValue VData, SelectionDAG &DAG, 112 bool ImageStore = false) const; 113 114 /// Converts \p Op, which must be of floating point type, to the 115 /// floating point type \p VT, by either extending or truncating it. 116 SDValue getFPExtOrFPRound(SelectionDAG &DAG, 117 SDValue Op, 118 const SDLoc &DL, 119 EVT VT) const; 120 121 SDValue convertArgType( 122 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val, 123 bool Signed, const ISD::InputArg *Arg = nullptr) const; 124 125 /// Custom lowering for ISD::FP_ROUND for MVT::f16. 126 SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 127 SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const; 128 SDValue lowerXMULO(SDValue Op, SelectionDAG &DAG) const; 129 130 SDValue getSegmentAperture(unsigned AS, const SDLoc &DL, 131 SelectionDAG &DAG) const; 132 133 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const; 134 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 135 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 136 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 137 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 138 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 139 SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const; 140 SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const; 141 142 SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const; 143 144 SDValue performUCharToFloatCombine(SDNode *N, 145 DAGCombinerInfo &DCI) const; 146 SDValue performSHLPtrCombine(SDNode *N, 147 unsigned AS, 148 EVT MemVT, 149 DAGCombinerInfo &DCI) const; 150 151 SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const; 152 153 SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL, 154 unsigned Opc, SDValue LHS, 155 const ConstantSDNode *CRHS) const; 156 157 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const; 158 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const; 159 SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const; 160 SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const; 161 SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const; 162 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const; 163 SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT, 164 const APFloat &C) const; 165 SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const; 166 167 SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, 168 SDValue Op0, SDValue Op1) const; 169 SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, 170 SDValue Op0, SDValue Op1, bool Signed) const; 171 SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const; 172 SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const; 173 SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const; 174 SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const; 175 SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const; 176 177 SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const; 178 unsigned getFusedOpcode(const SelectionDAG &DAG, 179 const SDNode *N0, const SDNode *N1) const; 180 SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; 181 SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const; 182 SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; 183 SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; 184 SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; 185 SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const; 186 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const; 187 SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const; 188 SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const; 189 SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const; 190 191 bool isLegalFlatAddressingMode(const AddrMode &AM) const; 192 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const; 193 194 unsigned isCFIntrinsic(const SDNode *Intr) const; 195 196 public: 197 /// \returns True if fixup needs to be emitted for given global value \p GV, 198 /// false otherwise. 199 bool shouldEmitFixup(const GlobalValue *GV) const; 200 201 /// \returns True if GOT relocation needs to be emitted for given global value 202 /// \p GV, false otherwise. 203 bool shouldEmitGOTReloc(const GlobalValue *GV) const; 204 205 /// \returns True if PC-relative relocation needs to be emitted for given 206 /// global value \p GV, false otherwise. 207 bool shouldEmitPCReloc(const GlobalValue *GV) const; 208 209 /// \returns true if this should use a literal constant for an LDS address, 210 /// and not emit a relocation for an LDS global. 211 bool shouldUseLDSConstAddress(const GlobalValue *GV) const; 212 213 /// Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be 214 /// expanded into a set of cmp/select instructions. 215 static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem, 216 bool IsDivergentIdx); 217 218 private: 219 // Analyze a combined offset from an amdgcn_buffer_ intrinsic and store the 220 // three offsets (voffset, soffset and instoffset) into the SDValue[3] array 221 // pointed to by Offsets. 222 /// \returns 0 If there is a non-constant offset or if the offset is 0. 223 /// Otherwise returns the constant offset. 224 unsigned setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG, 225 SDValue *Offsets, Align Alignment = Align(4)) const; 226 227 // Handle 8 bit and 16 bit buffer loads 228 SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL, 229 ArrayRef<SDValue> Ops, MemSDNode *M) const; 230 231 // Handle 8 bit and 16 bit buffer stores 232 SDValue handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType, 233 SDLoc DL, SDValue Ops[], 234 MemSDNode *M) const; 235 236 public: 237 SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI); 238 239 const GCNSubtarget *getSubtarget() const; 240 241 bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, 242 EVT SrcVT) const override; 243 244 bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override; 245 246 bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, 247 MachineFunction &MF, 248 unsigned IntrinsicID) const override; 249 250 bool getAddrModeArguments(IntrinsicInst * /*I*/, 251 SmallVectorImpl<Value*> &/*Ops*/, 252 Type *&/*AccessTy*/) const override; 253 254 bool isLegalGlobalAddressingMode(const AddrMode &AM) const; 255 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 256 unsigned AS, 257 Instruction *I = nullptr) const override; 258 259 bool canMergeStoresTo(unsigned AS, EVT MemVT, 260 const SelectionDAG &DAG) const override; 261 262 bool allowsMisalignedMemoryAccessesImpl( 263 unsigned Size, unsigned AddrSpace, Align Alignment, 264 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 265 bool *IsFast = nullptr) const; 266 267 bool allowsMisalignedMemoryAccesses( 268 LLT Ty, unsigned AddrSpace, Align Alignment, 269 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 270 bool *IsFast = nullptr) const override { 271 if (IsFast) 272 *IsFast = false; 273 return allowsMisalignedMemoryAccessesImpl(Ty.getSizeInBits(), AddrSpace, 274 Alignment, Flags, IsFast); 275 } 276 277 bool allowsMisalignedMemoryAccesses( 278 EVT VT, unsigned AS, unsigned Alignment, 279 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 280 bool *IsFast = nullptr) const override; 281 282 EVT getOptimalMemOpType(const MemOp &Op, 283 const AttributeList &FuncAttributes) const override; 284 285 bool isMemOpUniform(const SDNode *N) const; 286 bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const; 287 isNonGlobalAddrSpace(unsigned AS)288 static bool isNonGlobalAddrSpace(unsigned AS) { 289 return AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::REGION_ADDRESS || 290 AS == AMDGPUAS::PRIVATE_ADDRESS; 291 } 292 293 bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 294 295 TargetLoweringBase::LegalizeTypeAction 296 getPreferredVectorAction(MVT VT) const override; 297 298 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 299 Type *Ty) const override; 300 301 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override; 302 303 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 304 305 bool supportSplitCSR(MachineFunction *MF) const override; 306 void initializeSplitCSR(MachineBasicBlock *Entry) const override; 307 void insertCopiesSplitCSR( 308 MachineBasicBlock *Entry, 309 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 310 311 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 312 bool isVarArg, 313 const SmallVectorImpl<ISD::InputArg> &Ins, 314 const SDLoc &DL, SelectionDAG &DAG, 315 SmallVectorImpl<SDValue> &InVals) const override; 316 317 bool CanLowerReturn(CallingConv::ID CallConv, 318 MachineFunction &MF, bool isVarArg, 319 const SmallVectorImpl<ISD::OutputArg> &Outs, 320 LLVMContext &Context) const override; 321 322 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 323 const SmallVectorImpl<ISD::OutputArg> &Outs, 324 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 325 SelectionDAG &DAG) const override; 326 327 void passSpecialInputs( 328 CallLoweringInfo &CLI, 329 CCState &CCInfo, 330 const SIMachineFunctionInfo &Info, 331 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass, 332 SmallVectorImpl<SDValue> &MemOpChains, 333 SDValue Chain) const; 334 335 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 336 CallingConv::ID CallConv, bool isVarArg, 337 const SmallVectorImpl<ISD::InputArg> &Ins, 338 const SDLoc &DL, SelectionDAG &DAG, 339 SmallVectorImpl<SDValue> &InVals, bool isThisReturn, 340 SDValue ThisVal) const; 341 342 bool mayBeEmittedAsTailCall(const CallInst *) const override; 343 344 bool isEligibleForTailCallOptimization( 345 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, 346 const SmallVectorImpl<ISD::OutputArg> &Outs, 347 const SmallVectorImpl<SDValue> &OutVals, 348 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const; 349 350 SDValue LowerCall(CallLoweringInfo &CLI, 351 SmallVectorImpl<SDValue> &InVals) const override; 352 353 SDValue lowerDYNAMIC_STACKALLOCImpl(SDValue Op, SelectionDAG &DAG) const; 354 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 355 356 Register getRegisterByName(const char* RegName, LLT VT, 357 const MachineFunction &MF) const override; 358 359 MachineBasicBlock *splitKillBlock(MachineInstr &MI, 360 MachineBasicBlock *BB) const; 361 362 void bundleInstWithWaitcnt(MachineInstr &MI) const; 363 MachineBasicBlock *emitGWSMemViolTestLoop(MachineInstr &MI, 364 MachineBasicBlock *BB) const; 365 366 MachineBasicBlock * 367 EmitInstrWithCustomInserter(MachineInstr &MI, 368 MachineBasicBlock *BB) const override; 369 370 bool hasBitPreservingFPLogic(EVT VT) const override; 371 bool enableAggressiveFMAFusion(EVT VT) const override; 372 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 373 EVT VT) const override; 374 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override; 375 LLT getPreferredShiftAmountTy(LLT Ty) const override; 376 377 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 378 EVT VT) const override; 379 bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override; 380 381 SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 382 SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 383 SDValue splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 384 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 385 386 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 387 SelectionDAG &DAG) const override; 388 389 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 390 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override; 391 void AdjustInstrPostInstrSelection(MachineInstr &MI, 392 SDNode *Node) const override; 393 394 SDNode *legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const; 395 396 MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, 397 SDValue Ptr) const; 398 MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, 399 uint32_t RsrcDword1, uint64_t RsrcDword2And3) const; 400 std::pair<unsigned, const TargetRegisterClass *> 401 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 402 StringRef Constraint, MVT VT) const override; 403 ConstraintType getConstraintType(StringRef Constraint) const override; 404 void LowerAsmOperandForConstraint(SDValue Op, 405 std::string &Constraint, 406 std::vector<SDValue> &Ops, 407 SelectionDAG &DAG) const override; 408 bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const; 409 bool checkAsmConstraintVal(SDValue Op, 410 const std::string &Constraint, 411 uint64_t Val) const; 412 bool checkAsmConstraintValA(SDValue Op, 413 uint64_t Val, 414 unsigned MaxSize = 64) const; 415 SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, 416 SDValue V) const; 417 418 void finalizeLowering(MachineFunction &MF) const override; 419 420 void computeKnownBitsForFrameIndex(int FrameIdx, 421 KnownBits &Known, 422 const MachineFunction &MF) const override; 423 void computeKnownBitsForTargetInstr(GISelKnownBits &Analysis, Register R, 424 KnownBits &Known, 425 const APInt &DemandedElts, 426 const MachineRegisterInfo &MRI, 427 unsigned Depth = 0) const override; 428 429 Align computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R, 430 const MachineRegisterInfo &MRI, 431 unsigned Depth = 0) const override; 432 bool isSDNodeSourceOfDivergence(const SDNode *N, 433 FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override; 434 435 bool isCanonicalized(SelectionDAG &DAG, SDValue Op, 436 unsigned MaxDepth = 5) const; 437 bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const; 438 439 bool isKnownNeverNaNForTargetNode(SDValue Op, 440 const SelectionDAG &DAG, 441 bool SNaN = false, 442 unsigned Depth = 0) const override; 443 AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override; 444 445 virtual const TargetRegisterClass * 446 getRegClassFor(MVT VT, bool isDivergent) const override; 447 virtual bool requiresUniformRegister(MachineFunction &MF, 448 const Value *V) const override; 449 Align getPrefLoopAlignment(MachineLoop *ML) const override; 450 451 void allocateHSAUserSGPRs(CCState &CCInfo, 452 MachineFunction &MF, 453 const SIRegisterInfo &TRI, 454 SIMachineFunctionInfo &Info) const; 455 456 void allocateSystemSGPRs(CCState &CCInfo, 457 MachineFunction &MF, 458 SIMachineFunctionInfo &Info, 459 CallingConv::ID CallConv, 460 bool IsShader) const; 461 462 void allocateSpecialEntryInputVGPRs(CCState &CCInfo, 463 MachineFunction &MF, 464 const SIRegisterInfo &TRI, 465 SIMachineFunctionInfo &Info) const; 466 void allocateSpecialInputSGPRs( 467 CCState &CCInfo, 468 MachineFunction &MF, 469 const SIRegisterInfo &TRI, 470 SIMachineFunctionInfo &Info) const; 471 472 void allocateSpecialInputVGPRs(CCState &CCInfo, 473 MachineFunction &MF, 474 const SIRegisterInfo &TRI, 475 SIMachineFunctionInfo &Info) const; 476 void allocateSpecialInputVGPRsFixed(CCState &CCInfo, 477 MachineFunction &MF, 478 const SIRegisterInfo &TRI, 479 SIMachineFunctionInfo &Info) const; 480 481 std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL, 482 Type *Ty) const; 483 }; 484 485 } // End namespace llvm 486 487 #endif 488