• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s 2>%t | FileCheck %s
2; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
3
4; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
5; WARN-NOT: warning
6
7
8;
9; CDOT
10;
11
12define <vscale x 4 x i32> @cdot_s(<vscale x 4 x i32> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {
13; CHECK-LABEL: cdot_s:
14; CHECK: cdot z0.s, z1.b, z2.b, #0
15; CHECK-NEXT: ret
16  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.cdot.nxv4i32(<vscale x 4 x i32> %a,
17                                                                <vscale x 16 x i8> %b,
18                                                                <vscale x 16 x i8> %c,
19                                                                i32 0)
20  ret <vscale x 4 x i32> %out
21}
22
23define <vscale x 2 x i64> @cdot_d(<vscale x 2 x i64> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {
24; CHECK-LABEL: cdot_d:
25; CHECK: cdot z0.d, z1.h, z2.h, #90
26; CHECK-NEXT: ret
27  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.cdot.nxv2i64(<vscale x 2 x i64> %a,
28                                                                <vscale x 8 x i16> %b,
29                                                                <vscale x 8 x i16> %c,
30                                                                i32 90)
31  ret <vscale x 2 x i64> %out
32}
33
34;
35; CDOT(indexed)
36;
37
38define <vscale x 4 x i32> @cdot_s_idx(<vscale x 4 x i32> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {
39; CHECK-LABEL: cdot_s_idx:
40; CHECK: cdot z0.s, z1.b, z2.b[0], #180
41; CHECK-NEXT: ret
42  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.cdot.lane.nxv4i32(<vscale x 4 x i32> %a,
43                                                                     <vscale x 16 x i8> %b,
44                                                                     <vscale x 16 x i8> %c,
45                                                                     i32 0, i32 180)
46  ret <vscale x 4 x i32> %out
47}
48
49
50define <vscale x 2 x i64> @cdot_d_idx(<vscale x 2 x i64> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {
51; CHECK-LABEL: cdot_d_idx:
52; CHECK: cdot z0.d, z1.h, z2.h[1], #270
53; CHECK-NEXT: ret
54  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.cdot.lane.nxv2i64(<vscale x 2 x i64> %a,
55                                                                     <vscale x 8 x i16> %b,
56                                                                     <vscale x 8 x i16> %c,
57                                                                     i32 1, i32 270)
58  ret <vscale x 2 x i64> %out
59}
60
61
62declare <vscale x 4 x i32> @llvm.aarch64.sve.cdot.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32)
63declare <vscale x 2 x i64> @llvm.aarch64.sve.cdot.nxv2i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32)
64declare <vscale x 4 x i32> @llvm.aarch64.sve.cdot.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32, i32)
65declare <vscale x 2 x i64> @llvm.aarch64.sve.cdot.lane.nxv2i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32, i32)
66