1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 3# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 4 5--- 6name: cos_s32_vs 7legalized: true 8regBankSelected: true 9tracksRegLiveness: true 10 11body: | 12 bb.0: 13 liveins: $sgpr0 14 15 ; CHECK-LABEL: name: cos_s32_vs 16 ; CHECK: liveins: $sgpr0 17 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 18 ; CHECK: %1:vgpr_32 = nofpexcept V_COS_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec 19 ; CHECK: S_ENDPGM 0, implicit %1 20 %0:sgpr(s32) = COPY $sgpr0 21 %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %0 22 S_ENDPGM 0, implicit %1 23... 24 25--- 26name: cos_s32_vv 27legalized: true 28regBankSelected: true 29tracksRegLiveness: true 30 31body: | 32 bb.0: 33 liveins: $vgpr0 34 35 ; CHECK-LABEL: name: cos_s32_vv 36 ; CHECK: liveins: $vgpr0 37 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 38 ; CHECK: %1:vgpr_32 = nofpexcept V_COS_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec 39 ; CHECK: S_ENDPGM 0, implicit %1 40 %0:vgpr(s32) = COPY $vgpr0 41 %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %0 42 S_ENDPGM 0, implicit %1 43... 44