1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s 3 4define amdgpu_kernel void @test_wave64(i32 %arg0, i64 %saved) { 5; GCN-LABEL: test_wave64: 6; GCN: ; %bb.0: ; %entry 7; GCN-NEXT: s_load_dword s2, s[4:5], 0x0 8; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8 9; GCN-NEXT: s_waitcnt lgkmcnt(0) 10; GCN-NEXT: s_cmp_lg_u32 s2, 0 11; GCN-NEXT: s_cselect_b32 s2, 1, 0 12; GCN-NEXT: s_and_b32 s2, s2, 1 13; GCN-NEXT: s_cmp_lg_u32 s2, 0 14; GCN-NEXT: s_cbranch_scc1 BB0_2 15; GCN-NEXT: ; %bb.1: ; %mid 16; GCN-NEXT: v_mov_b32_e32 v0, 0 17; GCN-NEXT: global_store_dword v[0:1], v0, off 18; GCN-NEXT: BB0_2: ; %bb 19; GCN-NEXT: s_or_b64 exec, exec, s[0:1] 20; GCN-NEXT: v_mov_b32_e32 v0, 0 21; GCN-NEXT: global_store_dword v[0:1], v0, off 22; GCN-NEXT: s_endpgm 23entry: 24 %cond = icmp eq i32 %arg0, 0 25 br i1 %cond, label %mid, label %bb 26 27mid: 28 store volatile i32 0, i32 addrspace(1)* undef 29 br label %bb 30 31bb: 32 call void @llvm.amdgcn.end.cf.i64(i64 %saved) 33 store volatile i32 0, i32 addrspace(1)* undef 34 ret void 35} 36 37declare void @llvm.amdgcn.end.cf.i64(i64 %val) 38