1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii < %s | FileCheck -check-prefixes=GCN,CI %s 3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,VI %s 4; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s 5 6define double @v_trig_preop_f64(double %a, i32 %b) { 7; GCN-LABEL: v_trig_preop_f64: 8; GCN: ; %bb.0: 9; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 10; GCN-NEXT: v_trig_preop_f64 v[0:1], v[0:1], v2 11; GCN-NEXT: s_setpc_b64 s[30:31] 12 %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 %b) 13 ret double %result 14} 15 16define double @v_trig_preop_f64_imm(double %a, i32 %b) { 17; GCN-LABEL: v_trig_preop_f64_imm: 18; GCN: ; %bb.0: 19; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 20; GCN-NEXT: v_trig_preop_f64 v[0:1], v[0:1], 7 21; GCN-NEXT: s_setpc_b64 s[30:31] 22 %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 7) 23 ret double %result 24} 25 26define amdgpu_kernel void @s_trig_preop_f64(double %a, i32 %b) { 27; CI-LABEL: s_trig_preop_f64: 28; CI: ; %bb.0: 29; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 30; CI-NEXT: s_load_dword s2, s[4:5], 0x2 31; CI-NEXT: s_waitcnt lgkmcnt(0) 32; CI-NEXT: v_mov_b32_e32 v0, s2 33; CI-NEXT: v_trig_preop_f64 v[0:1], s[0:1], v0 34; CI-NEXT: flat_store_dwordx2 v[0:1], v[0:1] 35; CI-NEXT: s_endpgm 36; 37; VI-LABEL: s_trig_preop_f64: 38; VI: ; %bb.0: 39; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 40; VI-NEXT: s_load_dword s2, s[4:5], 0x8 41; VI-NEXT: s_waitcnt lgkmcnt(0) 42; VI-NEXT: v_mov_b32_e32 v0, s2 43; VI-NEXT: v_trig_preop_f64 v[0:1], s[0:1], v0 44; VI-NEXT: flat_store_dwordx2 v[0:1], v[0:1] 45; VI-NEXT: s_endpgm 46; 47; GFX9-LABEL: s_trig_preop_f64: 48; GFX9: ; %bb.0: 49; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 50; GFX9-NEXT: s_load_dword s2, s[4:5], 0x8 51; GFX9-NEXT: s_waitcnt lgkmcnt(0) 52; GFX9-NEXT: v_mov_b32_e32 v0, s2 53; GFX9-NEXT: v_trig_preop_f64 v[0:1], s[0:1], v0 54; GFX9-NEXT: flat_store_dwordx2 v[0:1], v[0:1] 55; GFX9-NEXT: s_endpgm 56 %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 %b) 57 store volatile double %result, double* undef 58 ret void 59} 60 61define amdgpu_kernel void @s_trig_preop_f64_imm(double %a, i32 %b) { 62; GCN-LABEL: s_trig_preop_f64_imm: 63; GCN: ; %bb.0: 64; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 65; GCN-NEXT: s_waitcnt lgkmcnt(0) 66; GCN-NEXT: v_trig_preop_f64 v[0:1], s[0:1], 7 67; GCN-NEXT: flat_store_dwordx2 v[0:1], v[0:1] 68; GCN-NEXT: s_endpgm 69 %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 7) 70 store volatile double %result, double* undef 71 ret void 72} 73 74declare double @llvm.amdgcn.trig.preop.f64(double, i32) #0 75 76attributes #0 = { nounwind readnone speculatable } 77