1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2; RUN: llc -global-isel -march=amdgcn -mcpu=hawaii -stop-after=instruction-select -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s 3 4define amdgpu_ps float @wqm_f32(float %val) { 5 ; GCN-LABEL: name: wqm_f32 6 ; GCN: bb.1 (%ir-block.0): 7 ; GCN: liveins: $vgpr0 8 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 9 ; GCN: [[WQM:%[0-9]+]]:vgpr_32 = WQM [[COPY]], implicit $exec 10 ; GCN: $vgpr0 = COPY [[WQM]] 11 ; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0 12 %ret = call float @llvm.amdgcn.wqm.f32(float %val) 13 ret float %ret 14} 15 16define amdgpu_ps float @wqm_v2f16(float %arg) { 17 ; GCN-LABEL: name: wqm_v2f16 18 ; GCN: bb.1 (%ir-block.0): 19 ; GCN: liveins: $vgpr0 20 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 21 ; GCN: [[WQM:%[0-9]+]]:vgpr_32 = WQM [[COPY]], implicit $exec 22 ; GCN: $vgpr0 = COPY [[WQM]] 23 ; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0 24 %val = bitcast float %arg to <2 x half> 25 %ret = call <2 x half> @llvm.amdgcn.wqm.v2f16(<2 x half> %val) 26 %bc = bitcast <2 x half> %ret to float 27 ret float %bc 28} 29 30define amdgpu_ps <2 x float> @wqm_f64(double %val) { 31 ; GCN-LABEL: name: wqm_f64 32 ; GCN: bb.1 (%ir-block.0): 33 ; GCN: liveins: $vgpr0, $vgpr1 34 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 35 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 36 ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 37 ; GCN: [[WQM:%[0-9]+]]:vreg_64 = WQM [[REG_SEQUENCE]], implicit $exec 38 ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[WQM]].sub0 39 ; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[WQM]].sub1 40 ; GCN: $vgpr0 = COPY [[COPY2]] 41 ; GCN: $vgpr1 = COPY [[COPY3]] 42 ; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 43 %ret = call double @llvm.amdgcn.wqm.f64(double %val) 44 %bitcast = bitcast double %ret to <2 x float> 45 ret <2 x float> %bitcast 46} 47 48; TODO 49; define amdgpu_ps float @wqm_i1_vcc(float %val) { 50; %vcc = fcmp oeq float %val, 0.0 51; %ret = call i1 @llvm.amdgcn.wqm.i1(i1 %vcc) 52; %select = select i1 %ret, float 1.0, float 0.0 53; ret float %select 54; } 55 56define amdgpu_ps <3 x float> @wqm_v3f32(<3 x float> %val) { 57 ; GCN-LABEL: name: wqm_v3f32 58 ; GCN: bb.1 (%ir-block.0): 59 ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2 60 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 61 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 62 ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 63 ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2 64 ; GCN: [[WQM:%[0-9]+]]:vreg_96 = WQM [[REG_SEQUENCE]], implicit $exec 65 ; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[WQM]].sub0 66 ; GCN: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[WQM]].sub1 67 ; GCN: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[WQM]].sub2 68 ; GCN: $vgpr0 = COPY [[COPY3]] 69 ; GCN: $vgpr1 = COPY [[COPY4]] 70 ; GCN: $vgpr2 = COPY [[COPY5]] 71 ; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 72 %ret = call <3 x float> @llvm.amdgcn.wqm.v3f32(<3 x float> %val) 73 ret <3 x float> %ret 74} 75 76declare i1 @llvm.amdgcn.wqm.i1(i1) #0 77declare float @llvm.amdgcn.wqm.f32(float) #0 78declare <2 x half> @llvm.amdgcn.wqm.v2f16(<2 x half>) #0 79declare <3 x float> @llvm.amdgcn.wqm.v3f32(<3 x float>) #0 80declare double @llvm.amdgcn.wqm.f64(double) #0 81 82attributes #0 = { nounwind readnone speculatable } 83