1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=SI -check-prefix=FUNC %s 2; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=CI -check-prefix=FUNC %s 3; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=CI -check-prefix=FUNC %s 4 5declare double @llvm.ceil.f64(double) nounwind readnone 6declare <2 x double> @llvm.ceil.v2f64(<2 x double>) nounwind readnone 7declare <3 x double> @llvm.ceil.v3f64(<3 x double>) nounwind readnone 8declare <4 x double> @llvm.ceil.v4f64(<4 x double>) nounwind readnone 9declare <8 x double> @llvm.ceil.v8f64(<8 x double>) nounwind readnone 10declare <16 x double> @llvm.ceil.v16f64(<16 x double>) nounwind readnone 11 12; FUNC-LABEL: {{^}}fceil_f64: 13; CI: v_ceil_f64_e32 14; SI: s_bfe_u32 [[SEXP:s[0-9]+]], {{s[0-9]+}}, 0xb0014 15; SI-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000 16; FIXME: We should be using s_addk_i32 here, but the reg allocation hints 17; are not always followed. 18; SI-DAG: s_add_i32 [[SEXP0:s[0-9]+]], [[SEXP]], 0xfffffc01 19; SI-DAG: s_lshr_b64 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], [[SEXP0]] 20; SI-DAG: s_andn2_b64 21; SI-DAG: cmp_gt_i32 22; SI-DAG: cndmask_b32 23; SI-DAG: cndmask_b32 24; SI-DAG: cmp_lt_i32 25; SI-DAG: cndmask_b32 26; SI-DAG: cndmask_b32 27; SI-DAG: v_cmp_gt_f64 28; SI-DAG: v_cmp_lg_f64 29; SI-DAG: v_cndmask_b32 30; SI: v_cndmask_b32 31; SI: v_add_f64 32; SI: s_endpgm 33define amdgpu_kernel void @fceil_f64(double addrspace(1)* %out, double %x) { 34 %y = call double @llvm.ceil.f64(double %x) nounwind readnone 35 store double %y, double addrspace(1)* %out 36 ret void 37} 38 39; FUNC-LABEL: {{^}}fceil_v2f64: 40; CI: v_ceil_f64_e32 41; CI: v_ceil_f64_e32 42define amdgpu_kernel void @fceil_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %x) { 43 %y = call <2 x double> @llvm.ceil.v2f64(<2 x double> %x) nounwind readnone 44 store <2 x double> %y, <2 x double> addrspace(1)* %out 45 ret void 46} 47 48; FIXME-FUNC-LABEL: {{^}}fceil_v3f64: 49; FIXME-CI: v_ceil_f64_e32 50; FIXME-CI: v_ceil_f64_e32 51; FIXME-CI: v_ceil_f64_e32 52; define amdgpu_kernel void @fceil_v3f64(<3 x double> addrspace(1)* %out, <3 x double> %x) { 53; %y = call <3 x double> @llvm.ceil.v3f64(<3 x double> %x) nounwind readnone 54; store <3 x double> %y, <3 x double> addrspace(1)* %out 55; ret void 56; } 57 58; FUNC-LABEL: {{^}}fceil_v4f64: 59; CI: v_ceil_f64_e32 60; CI: v_ceil_f64_e32 61; CI: v_ceil_f64_e32 62; CI: v_ceil_f64_e32 63define amdgpu_kernel void @fceil_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %x) { 64 %y = call <4 x double> @llvm.ceil.v4f64(<4 x double> %x) nounwind readnone 65 store <4 x double> %y, <4 x double> addrspace(1)* %out 66 ret void 67} 68 69; FUNC-LABEL: {{^}}fceil_v8f64: 70; CI: v_ceil_f64_e32 71; CI: v_ceil_f64_e32 72; CI: v_ceil_f64_e32 73; CI: v_ceil_f64_e32 74; CI: v_ceil_f64_e32 75; CI: v_ceil_f64_e32 76; CI: v_ceil_f64_e32 77; CI: v_ceil_f64_e32 78define amdgpu_kernel void @fceil_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %x) { 79 %y = call <8 x double> @llvm.ceil.v8f64(<8 x double> %x) nounwind readnone 80 store <8 x double> %y, <8 x double> addrspace(1)* %out 81 ret void 82} 83 84; FUNC-LABEL: {{^}}fceil_v16f64: 85; CI: v_ceil_f64_e32 86; CI: v_ceil_f64_e32 87; CI: v_ceil_f64_e32 88; CI: v_ceil_f64_e32 89; CI: v_ceil_f64_e32 90; CI: v_ceil_f64_e32 91; CI: v_ceil_f64_e32 92; CI: v_ceil_f64_e32 93; CI: v_ceil_f64_e32 94; CI: v_ceil_f64_e32 95; CI: v_ceil_f64_e32 96; CI: v_ceil_f64_e32 97; CI: v_ceil_f64_e32 98; CI: v_ceil_f64_e32 99; CI: v_ceil_f64_e32 100; CI: v_ceil_f64_e32 101define amdgpu_kernel void @fceil_v16f64(<16 x double> addrspace(1)* %out, <16 x double> %x) { 102 %y = call <16 x double> @llvm.ceil.v16f64(<16 x double> %x) nounwind readnone 103 store <16 x double> %y, <16 x double> addrspace(1)* %out 104 ret void 105} 106