1; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s 2; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s 3; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -enable-var-scope -check-prefix=R600 -check-prefix=FUNC %s 4 5; FUNC-LABEL: {{^}}s_fneg_f32: 6; R600: -PV 7 8; GCN: s_load_dword [[VAL:s[0-9]+]] 9; GCN: s_xor_b32 [[NEG_VAL:s[0-9]+]], [[VAL]], 0x80000000 10; GCN: v_mov_b32_e32 v{{[0-9]+}}, [[NEG_VAL]] 11define amdgpu_kernel void @s_fneg_f32(float addrspace(1)* %out, float %in) { 12 %fneg = fsub float -0.000000e+00, %in 13 store float %fneg, float addrspace(1)* %out 14 ret void 15} 16 17; FUNC-LABEL: {{^}}s_fneg_v2f32: 18; R600: -PV 19; R600: -PV 20 21; GCN: s_brev_b32 [[SIGNBIT:s[0-9]+]], 1 22; GCN: s_xor_b32 23; GCN: s_xor_b32 24define amdgpu_kernel void @s_fneg_v2f32(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) { 25 %fneg = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %in 26 store <2 x float> %fneg, <2 x float> addrspace(1)* %out 27 ret void 28} 29 30; FUNC-LABEL: {{^}}s_fneg_v4f32: 31; R600: -PV 32; R600: -T 33; R600: -PV 34; R600: -PV 35 36; GCN: s_xor_b32 37; GCN: s_xor_b32 38; GCN: s_xor_b32 39; GCN: s_xor_b32 40define amdgpu_kernel void @s_fneg_v4f32(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) { 41 %fneg = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %in 42 store <4 x float> %fneg, <4 x float> addrspace(1)* %out 43 ret void 44} 45 46; DAGCombiner will transform: 47; (fneg (f32 bitcast (i32 a))) => (f32 bitcast (xor (i32 a), 0x80000000)) 48; unless the target returns true for isNegFree() 49 50; FUNC-LABEL: {{^}}fsub0_f32: 51 52; GCN: v_sub_f32_e64 v{{[0-9]}}, 0, s{{[0-9]+$}} 53 54; R600-NOT: XOR 55; R600: -KC0[2].Z 56define amdgpu_kernel void @fsub0_f32(float addrspace(1)* %out, i32 %in) { 57 %bc = bitcast i32 %in to float 58 %fsub = fsub float 0.0, %bc 59 store float %fsub, float addrspace(1)* %out 60 ret void 61} 62; FUNC-LABEL: {{^}}fneg_free_f32: 63; SI: s_load_dword [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb 64; VI: s_load_dword [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c 65 66; GCN: s_xor_b32 [[RES:s[0-9]+]], [[NEG_VALUE]], 0x80000000 67; GCN: v_mov_b32_e32 [[V_RES:v[0-9]+]], [[RES]] 68; GCN: buffer_store_dword [[V_RES]] 69 70; R600-NOT: XOR 71; R600: -PV.W 72define amdgpu_kernel void @fneg_free_f32(float addrspace(1)* %out, i32 %in) { 73 %bc = bitcast i32 %in to float 74 %fsub = fsub float -0.0, %bc 75 store float %fsub, float addrspace(1)* %out 76 ret void 77} 78 79; FUNC-LABEL: {{^}}fneg_fold_f32: 80; SI: s_load_dword [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb 81; VI: s_load_dword [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c 82; GCN-NOT: xor 83; GCN: v_mul_f32_e64 v{{[0-9]+}}, -[[NEG_VALUE]], [[NEG_VALUE]] 84define amdgpu_kernel void @fneg_fold_f32(float addrspace(1)* %out, float %in) { 85 %fsub = fsub float -0.0, %in 86 %fmul = fmul float %fsub, %in 87 store float %fmul, float addrspace(1)* %out 88 ret void 89} 90 91; Make sure we turn some integer operations back into fabs 92; FUNC-LABEL: {{^}}bitpreserve_fneg_f32: 93; GCN: v_mul_f32_e64 v{{[0-9]+}}, s{{[0-9]+}}, -4.0 94define amdgpu_kernel void @bitpreserve_fneg_f32(float addrspace(1)* %out, float %in) { 95 %in.bc = bitcast float %in to i32 96 %int.abs = xor i32 %in.bc, 2147483648 97 %bc = bitcast i32 %int.abs to float 98 %fadd = fmul float %bc, 4.0 99 store float %fadd, float addrspace(1)* %out 100 ret void 101} 102