1;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SICI 2;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=VI 3 4;CHECK-LABEL: {{^}}buffer_load: 5;CHECK: buffer_load_format_xyzw v[0:3], off, s[0:3], 0 6;CHECK: buffer_load_format_xyzw v[4:7], off, s[0:3], 0 glc 7;CHECK: buffer_load_format_xyzw v[8:11], off, s[0:3], 0 slc 8;CHECK: s_waitcnt 9define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) { 10main_body: 11 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0) 12 %data_glc = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i32 1) 13 %data_slc = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i32 2) 14 %r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0 15 %r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1 16 %r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2 17 ret {<4 x float>, <4 x float>, <4 x float>} %r2 18} 19 20;CHECK-LABEL: {{^}}buffer_load_immoffs: 21;CHECK: buffer_load_format_xyzw v[0:3], off, s[0:3], 0 offset:42 22;CHECK: s_waitcnt 23define amdgpu_ps <4 x float> @buffer_load_immoffs(<4 x i32> inreg) { 24main_body: 25 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %0, i32 42, i32 0, i32 0) 26 ret <4 x float> %data 27} 28 29;CHECK-LABEL: {{^}}buffer_load_immoffs_large: 30;CHECK-DAG: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], 60 offset:4092 31;CHECK-DAG: s_movk_i32 [[OFS1:s[0-9]+]], 0x7ffc 32;CHECK-DAG: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], [[OFS1]] offset:4092 33;CHECK-DAG: s_mov_b32 [[OFS2:s[0-9]+]], 0x8ffc 34;CHECK-DAG: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], [[OFS2]] offset:4 35;CHECK: s_waitcnt 36define amdgpu_ps <4 x float> @buffer_load_immoffs_large(<4 x i32> inreg) { 37main_body: 38 %d.0 = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %0, i32 4092, i32 60, i32 0) 39 %d.1 = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %0, i32 4092, i32 32764, i32 0) 40 %d.2 = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %0, i32 4, i32 36860, i32 0) 41 %d.3 = fadd <4 x float> %d.0, %d.1 42 %data = fadd <4 x float> %d.2, %d.3 43 ret <4 x float> %data 44} 45 46;CHECK-LABEL: {{^}}buffer_load_ofs: 47;CHECK: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 offen 48;CHECK: s_waitcnt 49define amdgpu_ps <4 x float> @buffer_load_ofs(<4 x i32> inreg, i32) { 50main_body: 51 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %0, i32 %1, i32 0, i32 0) 52 ret <4 x float> %data 53} 54 55;CHECK-LABEL: {{^}}buffer_load_ofs_imm: 56;CHECK: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 offen offset:60 57;CHECK: s_waitcnt 58define amdgpu_ps <4 x float> @buffer_load_ofs_imm(<4 x i32> inreg, i32) { 59main_body: 60 %ofs = add i32 %1, 60 61 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %0, i32 %ofs, i32 0, i32 0) 62 ret <4 x float> %data 63} 64 65;CHECK-LABEL: {{^}}buffer_load_x: 66;CHECK: buffer_load_format_x v0, off, s[0:3], 0 67;CHECK: s_waitcnt 68define amdgpu_ps float @buffer_load_x(<4 x i32> inreg %rsrc) { 69main_body: 70 %data = call float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32> %rsrc, i32 0, i32 0, i32 0) 71 ret float %data 72} 73 74;CHECK-LABEL: {{^}}buffer_load_xy: 75;CHECK: buffer_load_format_xy v[0:1], off, s[0:3], 0 76;CHECK: s_waitcnt 77define amdgpu_ps <2 x float> @buffer_load_xy(<4 x i32> inreg %rsrc) { 78main_body: 79 %data = call <2 x float> @llvm.amdgcn.raw.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 0, i32 0, i32 0) 80 ret <2 x float> %data 81} 82 83declare float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32>, i32, i32, i32) #0 84declare <2 x float> @llvm.amdgcn.raw.buffer.load.format.v2f32(<4 x i32>, i32, i32, i32) #0 85declare <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32>, i32, i32, i32) #0 86 87attributes #0 = { nounwind readonly } 88