1; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GCN %s 2; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI,CIVI,GCN %s 3; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CI,CIVI,GCN %s 4 5; GCN-LABEL: {{^}}s_abs_v2i16: 6; GFX9: s_load_dword [[VAL:s[0-9]+]] 7; GFX9: v_pk_sub_i16 [[SUB:v[0-9]+]], 0, [[VAL]] 8; GFX9: v_pk_max_i16 [[MAX:v[0-9]+]], [[VAL]], [[SUB]] 9; GFX9: v_pk_sub_u16 [[ADD:v[0-9]+]], [[MAX]], -2 op_sel_hi:[1,0] 10 11; CIVI: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 16 12; CIVI: s_sub_i32 13; CIVI: s_sub_i32 14; CIVI: s_max_i32 15; CIVI: s_max_i32 16; CIVI: s_add_i32 17; CIVI-DAG: s_add_i32 18; CIVI-DAG: s_and_b32 19; CIVI-DAG: s_or_b32 20define amdgpu_kernel void @s_abs_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %val) #0 { 21 %neg = sub <2 x i16> zeroinitializer, %val 22 %cond = icmp sgt <2 x i16> %val, %neg 23 %res = select <2 x i1> %cond, <2 x i16> %val, <2 x i16> %neg 24 %res2 = add <2 x i16> %res, <i16 2, i16 2> 25 store <2 x i16> %res2, <2 x i16> addrspace(1)* %out, align 4 26 ret void 27} 28 29; GCN-LABEL: {{^}}v_abs_v2i16: 30; GFX9: global_load_dword [[VAL:v[0-9]+]] 31; GFX9: v_pk_sub_i16 [[SUB:v[0-9]+]], 0, [[VAL]] 32; GFX9: v_pk_max_i16 [[MAX:v[0-9]+]], [[VAL]], [[SUB]] 33; GFX9: v_pk_sub_u16 [[ADD:v[0-9]+]], [[MAX]], -2 op_sel_hi:[1,0] 34 35; VI-DAG: v_mov_b32_e32 [[TWO:v[0-9]+]], 2 36; VI-DAG: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, 37; VI-DAG: v_sub_u16_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} 38; VI-DAG: v_sub_u16_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} 39; VI-DAG: v_max_i16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 40; VI-DAG: v_max_i16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 41; VI: v_add_u16_e32 v{{[0-9]+}}, 2, v{{[0-9]+}} 42; VI: v_add_u16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, [[TWO]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD 43; VI-NOT: v_and_b32 44; VI: v_or_b32_e32 45 46; CI: buffer_load_dword v 47; CI: v_lshrrev_b32_e32 48; CI-DAG: v_sub_i32_e32 49; CI-DAG: v_bfe_i32 50; CI-DAG: v_bfe_i32 51; CI-DAG: v_max_i32 52; CI-DAG: v_max_i32 53; CI-DAG: v_add_i32 54; CI-DAG: v_add_i32 55; CI-DAG: v_or_b32 56define amdgpu_kernel void @v_abs_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %src) #0 { 57 %tid = call i32 @llvm.amdgcn.workitem.id.x() 58 %gep.in = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %src, i32 %tid 59 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid 60 %val = load <2 x i16>, <2 x i16> addrspace(1)* %gep.in, align 4 61 %neg = sub <2 x i16> zeroinitializer, %val 62 %cond = icmp sgt <2 x i16> %val, %neg 63 %res = select <2 x i1> %cond, <2 x i16> %val, <2 x i16> %neg 64 %res2 = add <2 x i16> %res, <i16 2, i16 2> 65 store <2 x i16> %res2, <2 x i16> addrspace(1)* %gep.out, align 4 66 ret void 67} 68 69; GCN-LABEL: {{^}}s_abs_v2i16_2: 70; GFX9: s_load_dword [[VAL:s[0-9]+]] 71; GFX9: v_pk_sub_i16 [[SUB:v[0-9]+]], 0, [[VAL]] 72; GFX9: v_pk_max_i16 [[MAX:v[0-9]+]], [[VAL]], [[SUB]] 73; GFX9: v_pk_sub_u16 [[ADD:v[0-9]+]], [[MAX]], -2 op_sel_hi:[1,0] 74define amdgpu_kernel void @s_abs_v2i16_2(<2 x i16> addrspace(1)* %out, <2 x i16> %val) #0 { 75 %z0 = insertelement <2 x i16> undef, i16 0, i16 0 76 %z1 = insertelement <2 x i16> %z0, i16 0, i16 1 77 %t0 = insertelement <2 x i16> undef, i16 2, i16 0 78 %t1 = insertelement <2 x i16> %t0, i16 2, i16 1 79 %neg = sub <2 x i16> %z1, %val 80 %cond = icmp sgt <2 x i16> %val, %neg 81 %res = select <2 x i1> %cond, <2 x i16> %val, <2 x i16> %neg 82 %res2 = add <2 x i16> %res, %t1 83 store <2 x i16> %res2, <2 x i16> addrspace(1)* %out, align 4 84 ret void 85} 86 87; GCN-LABEL: {{^}}v_abs_v2i16_2: 88; GFX9: global_load_dword [[VAL:v[0-9]+]] 89; GFX9: v_pk_sub_i16 [[SUB:v[0-9]+]], 0, [[VAL]] 90; GFX9: v_pk_max_i16 [[MAX:v[0-9]+]], [[VAL]], [[SUB]] 91; GFX9: v_pk_sub_u16 [[ADD:v[0-9]+]], [[MAX]], -2 op_sel_hi:[1,0] 92define amdgpu_kernel void @v_abs_v2i16_2(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %src) #0 { 93 %z0 = insertelement <2 x i16> undef, i16 0, i16 0 94 %z1 = insertelement <2 x i16> %z0, i16 0, i16 1 95 %t0 = insertelement <2 x i16> undef, i16 2, i16 0 96 %t1 = insertelement <2 x i16> %t0, i16 2, i16 1 97 %tid = call i32 @llvm.amdgcn.workitem.id.x() 98 %gep.in = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %src, i32 %tid 99 %val = load <2 x i16>, <2 x i16> addrspace(1)* %gep.in, align 4 100 %neg = sub <2 x i16> %z1, %val 101 %cond = icmp sgt <2 x i16> %val, %neg 102 %res = select <2 x i1> %cond, <2 x i16> %val, <2 x i16> %neg 103 %res2 = add <2 x i16> %res, %t1 104 store <2 x i16> %res2, <2 x i16> addrspace(1)* %out, align 4 105 ret void 106} 107 108; GCN-LABEL: {{^}}s_abs_v4i16: 109; GFX9: s_load_dwordx2 s{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}}, s[0:1], 0x2c 110; GFX9-DAG: v_pk_sub_i16 [[SUB0:v[0-9]+]], 0, s[[VAL0]] 111; GFX9-DAG: v_pk_sub_i16 [[SUB1:v[0-9]+]], 0, s[[VAL1]] 112; GFX9-DAG: v_pk_max_i16 [[MAX0:v[0-9]+]], s[[VAL0]], [[SUB0]] 113; GFX9-DAG: v_pk_max_i16 [[MAX1:v[0-9]+]], s[[VAL1]], [[SUB1]] 114; GFX9-DAG: v_pk_sub_u16 [[ADD0:v[0-9]+]], [[MAX0]], -2 op_sel_hi:[1,0] 115; GFX9-DAG: v_pk_sub_u16 [[ADD1:v[0-9]+]], [[MAX1]], -2 op_sel_hi:[1,0] 116define amdgpu_kernel void @s_abs_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %val) #0 { 117 %z0 = insertelement <4 x i16> undef, i16 0, i16 0 118 %z1 = insertelement <4 x i16> %z0, i16 0, i16 1 119 %z2 = insertelement <4 x i16> %z1, i16 0, i16 2 120 %z3 = insertelement <4 x i16> %z2, i16 0, i16 3 121 %t0 = insertelement <4 x i16> undef, i16 2, i16 0 122 %t1 = insertelement <4 x i16> %t0, i16 2, i16 1 123 %t2 = insertelement <4 x i16> %t1, i16 2, i16 2 124 %t3 = insertelement <4 x i16> %t2, i16 2, i16 3 125 %neg = sub <4 x i16> %z3, %val 126 %cond = icmp sgt <4 x i16> %val, %neg 127 %res = select <4 x i1> %cond, <4 x i16> %val, <4 x i16> %neg 128 %res2 = add <4 x i16> %res, %t3 129 store <4 x i16> %res2, <4 x i16> addrspace(1)* %out, align 4 130 ret void 131} 132 133; GCN-LABEL: {{^}}v_abs_v4i16: 134; GFX9: global_load_dwordx2 v{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}} 135 136; GFX9-DAG: v_pk_sub_i16 [[SUB0:v[0-9]+]], 0, v[[VAL0]] 137; GFX9-DAG: v_pk_max_i16 [[MAX0:v[0-9]+]], v[[VAL0]], [[SUB0]] 138; GFX9-DAG: v_pk_sub_u16 [[ADD0:v[0-9]+]], [[MAX0]], -2 op_sel_hi:[1,0] 139 140; GFX9-DAG: v_pk_sub_i16 [[SUB1:v[0-9]+]], 0, v[[VAL1]] 141; GFX9-DAG: v_pk_max_i16 [[MAX1:v[0-9]+]], v[[VAL1]], [[SUB1]] 142; GFX9-DAG: v_pk_sub_u16 [[ADD1:v[0-9]+]], [[MAX1]], -2 op_sel_hi:[1,0] 143define amdgpu_kernel void @v_abs_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %src) #0 { 144 %z0 = insertelement <4 x i16> undef, i16 0, i16 0 145 %z1 = insertelement <4 x i16> %z0, i16 0, i16 1 146 %z2 = insertelement <4 x i16> %z1, i16 0, i16 2 147 %z3 = insertelement <4 x i16> %z2, i16 0, i16 3 148 %t0 = insertelement <4 x i16> undef, i16 2, i16 0 149 %t1 = insertelement <4 x i16> %t0, i16 2, i16 1 150 %t2 = insertelement <4 x i16> %t1, i16 2, i16 2 151 %t3 = insertelement <4 x i16> %t2, i16 2, i16 3 152 %tid = call i32 @llvm.amdgcn.workitem.id.x() 153 %gep.in = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %src, i32 %tid 154 %val = load <4 x i16>, <4 x i16> addrspace(1)* %gep.in, align 4 155 %neg = sub <4 x i16> %z3, %val 156 %cond = icmp sgt <4 x i16> %val, %neg 157 %res = select <4 x i1> %cond, <4 x i16> %val, <4 x i16> %neg 158 %res2 = add <4 x i16> %res, %t3 159 store <4 x i16> %res2, <4 x i16> addrspace(1)* %out, align 4 160 ret void 161} 162 163; GCN-LABEL: {{^}}s_min_max_v2i16: 164; GFX9: v_pk_max_i16 165; GFX9: v_pk_min_i16 166define amdgpu_kernel void @s_min_max_v2i16(<2 x i16> addrspace(1)* %out0, <2 x i16> addrspace(1)* %out1, <2 x i16> %val0, <2 x i16> %val1) #0 { 167 %cond0 = icmp sgt <2 x i16> %val0, %val1 168 %sel0 = select <2 x i1> %cond0, <2 x i16> %val0, <2 x i16> %val1 169 %sel1 = select <2 x i1> %cond0, <2 x i16> %val1, <2 x i16> %val0 170 171 store volatile <2 x i16> %sel0, <2 x i16> addrspace(1)* %out0, align 4 172 store volatile <2 x i16> %sel1, <2 x i16> addrspace(1)* %out1, align 4 173 ret void 174} 175 176; GCN-LABEL: {{^}}v_min_max_v2i16: 177; GFX9: v_pk_max_i16 178; GFX9: v_pk_min_i16 179define amdgpu_kernel void @v_min_max_v2i16(<2 x i16> addrspace(1)* %out0, <2 x i16> addrspace(1)* %out1, <2 x i16> addrspace(1)* %ptr0, <2 x i16> addrspace(1)* %ptr1) #0 { 180 %val0 = load volatile <2 x i16>, <2 x i16> addrspace(1)* %ptr0 181 %val1 = load volatile <2 x i16>, <2 x i16> addrspace(1)* %ptr1 182 183 %cond0 = icmp sgt <2 x i16> %val0, %val1 184 %sel0 = select <2 x i1> %cond0, <2 x i16> %val0, <2 x i16> %val1 185 %sel1 = select <2 x i1> %cond0, <2 x i16> %val1, <2 x i16> %val0 186 187 store volatile <2 x i16> %sel0, <2 x i16> addrspace(1)* %out0, align 4 188 store volatile <2 x i16> %sel1, <2 x i16> addrspace(1)* %out1, align 4 189 ret void 190} 191 192; GCN-LABEL: {{^}}s_min_max_v4i16: 193; GFX9-DAG: v_pk_max_i16 194; GFX9-DAG: v_pk_min_i16 195; GFX9-DAG: v_pk_max_i16 196; GFX9-DAG: v_pk_min_i16 197define amdgpu_kernel void @s_min_max_v4i16(<4 x i16> addrspace(1)* %out0, <4 x i16> addrspace(1)* %out1, <4 x i16> %val0, <4 x i16> %val1) #0 { 198 %cond0 = icmp sgt <4 x i16> %val0, %val1 199 %sel0 = select <4 x i1> %cond0, <4 x i16> %val0, <4 x i16> %val1 200 %sel1 = select <4 x i1> %cond0, <4 x i16> %val1, <4 x i16> %val0 201 202 store volatile <4 x i16> %sel0, <4 x i16> addrspace(1)* %out0, align 4 203 store volatile <4 x i16> %sel1, <4 x i16> addrspace(1)* %out1, align 4 204 ret void 205} 206 207; GCN-LABEL: {{^}}v_min_max_v2i16_user: 208define amdgpu_kernel void @v_min_max_v2i16_user(<2 x i16> addrspace(1)* %out0, <2 x i16> addrspace(1)* %out1, <2 x i16> addrspace(1)* %ptr0, <2 x i16> addrspace(1)* %ptr1) #0 { 209 %val0 = load volatile <2 x i16>, <2 x i16> addrspace(1)* %ptr0 210 %val1 = load volatile <2 x i16>, <2 x i16> addrspace(1)* %ptr1 211 212 %cond0 = icmp sgt <2 x i16> %val0, %val1 213 %sel0 = select <2 x i1> %cond0, <2 x i16> %val0, <2 x i16> %val1 214 %sel1 = select <2 x i1> %cond0, <2 x i16> %val1, <2 x i16> %val0 215 216 store volatile <2 x i16> %sel0, <2 x i16> addrspace(1)* %out0, align 4 217 store volatile <2 x i16> %sel1, <2 x i16> addrspace(1)* %out1, align 4 218 store volatile <2 x i1> %cond0, <2 x i1> addrspace(1)* undef 219 ret void 220} 221 222; GCN-LABEL: {{^}}u_min_max_v2i16: 223; GFX9: v_pk_max_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}} 224; GFX9: v_pk_min_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}} 225define amdgpu_kernel void @u_min_max_v2i16(<2 x i16> addrspace(1)* %out0, <2 x i16> addrspace(1)* %out1, <2 x i16> %val0, <2 x i16> %val1) nounwind { 226 %cond0 = icmp ugt <2 x i16> %val0, %val1 227 %sel0 = select <2 x i1> %cond0, <2 x i16> %val0, <2 x i16> %val1 228 %sel1 = select <2 x i1> %cond0, <2 x i16> %val1, <2 x i16> %val0 229 230 store volatile <2 x i16> %sel0, <2 x i16> addrspace(1)* %out0, align 4 231 store volatile <2 x i16> %sel1, <2 x i16> addrspace(1)* %out1, align 4 232 ret void 233} 234 235declare i32 @llvm.amdgcn.workitem.id.x() #1 236 237attributes #0 = { nounwind } 238attributes #1 = { nounwind readnone } 239