1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s 3; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s 4 5; =================================================================================== 6; V_XOR3_B32 7; =================================================================================== 8 9define amdgpu_ps float @xor3(i32 %a, i32 %b, i32 %c) { 10; GFX9-LABEL: xor3: 11; GFX9: ; %bb.0: 12; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1 13; GFX9-NEXT: v_xor_b32_e32 v0, v0, v2 14; GFX9-NEXT: ; return to shader part epilog 15; 16; GFX10-LABEL: xor3: 17; GFX10: ; %bb.0: 18; GFX10-NEXT: v_xor3_b32 v0, v0, v1, v2 19; GFX10-NEXT: ; return to shader part epilog 20 %x = xor i32 %a, %b 21 %result = xor i32 %x, %c 22 %bc = bitcast i32 %result to float 23 ret float %bc 24} 25 26define amdgpu_ps float @xor3_vgpr_b(i32 inreg %a, i32 %b, i32 inreg %c) { 27; GFX9-LABEL: xor3_vgpr_b: 28; GFX9: ; %bb.0: 29; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0 30; GFX9-NEXT: v_xor_b32_e32 v0, s3, v0 31; GFX9-NEXT: ; return to shader part epilog 32; 33; GFX10-LABEL: xor3_vgpr_b: 34; GFX10: ; %bb.0: 35; GFX10-NEXT: v_xor3_b32 v0, s2, v0, s3 36; GFX10-NEXT: ; return to shader part epilog 37 %x = xor i32 %a, %b 38 %result = xor i32 %x, %c 39 %bc = bitcast i32 %result to float 40 ret float %bc 41} 42 43define amdgpu_ps float @xor3_vgpr_all2(i32 %a, i32 %b, i32 %c) { 44; GFX9-LABEL: xor3_vgpr_all2: 45; GFX9: ; %bb.0: 46; GFX9-NEXT: v_xor_b32_e32 v1, v1, v2 47; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1 48; GFX9-NEXT: ; return to shader part epilog 49; 50; GFX10-LABEL: xor3_vgpr_all2: 51; GFX10: ; %bb.0: 52; GFX10-NEXT: v_xor3_b32 v0, v1, v2, v0 53; GFX10-NEXT: ; return to shader part epilog 54 %x = xor i32 %b, %c 55 %result = xor i32 %a, %x 56 %bc = bitcast i32 %result to float 57 ret float %bc 58} 59 60define amdgpu_ps float @xor3_vgpr_bc(i32 inreg %a, i32 %b, i32 %c) { 61; GFX9-LABEL: xor3_vgpr_bc: 62; GFX9: ; %bb.0: 63; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0 64; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1 65; GFX9-NEXT: ; return to shader part epilog 66; 67; GFX10-LABEL: xor3_vgpr_bc: 68; GFX10: ; %bb.0: 69; GFX10-NEXT: v_xor3_b32 v0, s2, v0, v1 70; GFX10-NEXT: ; return to shader part epilog 71 %x = xor i32 %a, %b 72 %result = xor i32 %x, %c 73 %bc = bitcast i32 %result to float 74 ret float %bc 75} 76 77define amdgpu_ps float @xor3_vgpr_const(i32 %a, i32 %b) { 78; GFX9-LABEL: xor3_vgpr_const: 79; GFX9: ; %bb.0: 80; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1 81; GFX9-NEXT: v_xor_b32_e32 v0, 16, v0 82; GFX9-NEXT: ; return to shader part epilog 83; 84; GFX10-LABEL: xor3_vgpr_const: 85; GFX10: ; %bb.0: 86; GFX10-NEXT: v_xor3_b32 v0, v0, v1, 16 87; GFX10-NEXT: ; return to shader part epilog 88 %x = xor i32 %a, %b 89 %result = xor i32 %x, 16 90 %bc = bitcast i32 %result to float 91 ret float %bc 92} 93 94define amdgpu_ps <2 x float> @xor3_multiuse_outer(i32 %a, i32 %b, i32 %c, i32 %x) { 95; GFX9-LABEL: xor3_multiuse_outer: 96; GFX9: ; %bb.0: 97; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1 98; GFX9-NEXT: v_xor_b32_e32 v0, v0, v2 99; GFX9-NEXT: v_mul_lo_u32 v1, v0, v3 100; GFX9-NEXT: ; return to shader part epilog 101; 102; GFX10-LABEL: xor3_multiuse_outer: 103; GFX10: ; %bb.0: 104; GFX10-NEXT: v_xor3_b32 v0, v0, v1, v2 105; GFX10-NEXT: v_mul_lo_u32 v1, v0, v3 106; GFX10-NEXT: ; return to shader part epilog 107 %inner = xor i32 %a, %b 108 %outer = xor i32 %inner, %c 109 %x1 = mul i32 %outer, %x 110 %r1 = insertelement <2 x i32> undef, i32 %outer, i32 0 111 %r0 = insertelement <2 x i32> %r1, i32 %x1, i32 1 112 %bc = bitcast <2 x i32> %r0 to <2 x float> 113 ret <2 x float> %bc 114} 115 116define amdgpu_ps <2 x float> @xor3_multiuse_inner(i32 %a, i32 %b, i32 %c) { 117; GFX9-LABEL: xor3_multiuse_inner: 118; GFX9: ; %bb.0: 119; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1 120; GFX9-NEXT: v_xor_b32_e32 v1, v0, v2 121; GFX9-NEXT: ; return to shader part epilog 122; 123; GFX10-LABEL: xor3_multiuse_inner: 124; GFX10: ; %bb.0: 125; GFX10-NEXT: v_xor_b32_e32 v0, v0, v1 126; GFX10-NEXT: v_xor_b32_e32 v1, v0, v2 127; GFX10-NEXT: ; return to shader part epilog 128 %inner = xor i32 %a, %b 129 %outer = xor i32 %inner, %c 130 %r1 = insertelement <2 x i32> undef, i32 %inner, i32 0 131 %r0 = insertelement <2 x i32> %r1, i32 %outer, i32 1 132 %bc = bitcast <2 x i32> %r0 to <2 x float> 133 ret <2 x float> %bc 134} 135 136; A case where uniform values end up in VGPRs -- we could use v_xor3_b32 here, 137; but we don't. 138define amdgpu_ps float @xor3_uniform_vgpr(float inreg %a, float inreg %b, float inreg %c) { 139; GFX9-LABEL: xor3_uniform_vgpr: 140; GFX9: ; %bb.0: 141; GFX9-NEXT: v_mov_b32_e32 v2, 0x40400000 142; GFX9-NEXT: v_add_f32_e64 v0, s2, 1.0 143; GFX9-NEXT: v_add_f32_e64 v1, s3, 2.0 144; GFX9-NEXT: v_add_f32_e32 v2, s4, v2 145; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1 146; GFX9-NEXT: v_xor_b32_e32 v0, v0, v2 147; GFX9-NEXT: ; return to shader part epilog 148; 149; GFX10-LABEL: xor3_uniform_vgpr: 150; GFX10: ; %bb.0: 151; GFX10-NEXT: v_add_f32_e64 v0, s2, 1.0 152; GFX10-NEXT: v_add_f32_e64 v1, s3, 2.0 153; GFX10-NEXT: v_add_f32_e64 v2, 0x40400000, s4 154; GFX10-NEXT: v_xor_b32_e32 v0, v0, v1 155; GFX10-NEXT: v_xor_b32_e32 v0, v0, v2 156; GFX10-NEXT: ; return to shader part epilog 157 %a1 = fadd float %a, 1.0 158 %b2 = fadd float %b, 2.0 159 %c3 = fadd float %c, 3.0 160 %bc.a = bitcast float %a1 to i32 161 %bc.b = bitcast float %b2 to i32 162 %bc.c = bitcast float %c3 to i32 163 %x = xor i32 %bc.a, %bc.b 164 %result = xor i32 %x, %bc.c 165 %bc = bitcast i32 %result to float 166 ret float %bc 167} 168