1; REQUIRES: asserts 2; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s 3 4; CHECK: ********** MI Scheduling ********** 5; We need second, post-ra scheduling to have VSTM instruction combined from single-stores 6; CHECK: ********** MI Scheduling ********** 7; CHECK: schedule starting 8; CHECK: VSTMDIA 9; CHECK: rdefs left 10; CHECK-NEXT: Latency : 2 11 12%bigVec = type [2 x double] 13 14@var = global %bigVec zeroinitializer 15 16define void @bar(%bigVec* %ptr) { 17 18 %tmp = load %bigVec, %bigVec* %ptr 19 store %bigVec %tmp, %bigVec* @var 20 21 ret void 22} 23 24