1; REQUIRES: asserts 2; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=R52_SCHED 3; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC 4; 5; Check the latency for instructions for both generic and cortex-r52. 6; Cortex-r52 machine model will cause the div to be sceduled before eor 7; as div takes more cycles to compute than eor. 8; 9; CHECK: ********** MI Scheduling ********** 10; CHECK: foo:%bb.0 entry 11; CHECK: EORrr 12; GENERIC: Latency : 1 13; R52_SCHED: Latency : 3 14; CHECK: MLA 15; GENERIC: Latency : 2 16; R52_SCHED: Latency : 4 17; CHECK: SDIV 18; GENERIC: Latency : 0 19; R52_SCHED: Latency : 8 20; CHECK: ** Final schedule for %bb.0 *** 21; GENERIC: EORrr 22; GENERIC: SDIV 23; R52_SCHED: SDIV 24; R52_SCHED: EORrr 25; CHECK: ********** INTERVALS ********** 26 27target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 28target triple = "armv8r-arm-none-eabi" 29 30; Function Attrs: norecurse nounwind readnone 31define hidden i32 @foo(i32 %a, i32 %b, i32 %c) local_unnamed_addr #0 { 32entry: 33 %xor = xor i32 %c, %b 34 %mul = mul nsw i32 %xor, %c 35 %add = add nsw i32 %mul, %a 36 %div = sdiv i32 %a, %b 37 %sub = sub i32 %add, %div 38 ret i32 %sub 39} 40