1# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-topdown 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=TOPDOWN 2# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-bottomup 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=BOTTOMUP 3# REQUIRES: asserts 4--- | 5 ; ModuleID = 'foo.ll' 6 source_filename = "foo.ll" 7 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 8 target triple = "arm---eabi" 9 10 %struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } 11 ; Function Attrs: nounwind 12 define <8 x i8> @foo(i8* %A) { 13 %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8.p0i8(i8* %A, i32 8) 14 %tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0 15 %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 1 16 %tmp4 = add <8 x i8> %tmp2, %tmp3 17 ret <8 x i8> %tmp4 18 } 19 declare %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8.p0i8(i8*, i32) 20 21# CHECK: ********** MI Scheduling ********** 22# CHECK: ScheduleDAGMILive::schedule starting 23# CHECK: SU(1): %1:qqpr = VLD4d8Pseudo %0:gpr, 8, 14, $noreg :: (load 32 from %ir.A, align 8) 24# CHECK: Latency : 8 25# CHECK: Single Issue : true; 26# CHECK: SU(2): %4:dpr = VADDv8i8 %1.dsub_0:qqpr, %1.dsub_1:qqpr, 14, $noreg 27# CHECK: Latency : 5 28# CHECK: Single Issue : false; 29# CHECK: SU(3): %5:gpr, %6:gpr = VMOVRRD %4:dpr, 14, $noreg 30# CHECK: Latency : 4 31# CHECK: Single Issue : false; 32 33# TOPDOWN: Scheduling SU(1) %1:qqpr = VLD4d8Pseudo 34# TOPDOWN: Bump cycle to end group 35# TOPDOWN: Scheduling SU(2) %4:dpr = VADDv8i8 36 37# BOTTOMUP: Scheduling SU(2) %4:dpr = VADDv8i8 38# BOTTOMUP: Scheduling SU(1) %1:qqpr = VLD4d8Pseudo 39# BOTTOMUP: Bump cycle to begin group 40 41... 42--- 43name: foo 44alignment: 4 45exposesReturnsTwice: false 46legalized: false 47regBankSelected: false 48selected: false 49tracksRegLiveness: true 50registers: 51 - { id: 0, class: gpr } 52 - { id: 1, class: qqpr } 53 - { id: 2, class: dpr } 54 - { id: 3, class: dpr } 55 - { id: 4, class: dpr } 56 - { id: 5, class: gpr } 57 - { id: 6, class: gpr } 58liveins: 59 - { reg: '$r0', virtual-reg: '%0' } 60frameInfo: 61 isFrameAddressTaken: false 62 isReturnAddressTaken: false 63 hasStackMap: false 64 hasPatchPoint: false 65 stackSize: 0 66 offsetAdjustment: 0 67 maxAlignment: 0 68 adjustsStack: false 69 hasCalls: false 70 maxCallFrameSize: 0 71 hasOpaqueSPAdjustment: false 72 hasVAStart: false 73 hasMustTailInVarArgFunc: false 74body: | 75 bb.0 (%ir-block.0): 76 liveins: $r0 77 78 %0 = COPY $r0 79 %1 = VLD4d8Pseudo %0, 8, 14, $noreg :: (load 32 from %ir.A, align 8) 80 %4 = VADDv8i8 %1.dsub_0, %1.dsub_1, 14, $noreg 81 %5, %6 = VMOVRRD %4, 14, $noreg 82 $r0 = COPY %5 83 $r1 = COPY %6 84 BX_RET 14, $noreg, implicit $r0, implicit killed $r1 85 86... 87