1; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s 2 3@llvm_mips_bmnzi_b_ARG1 = global <16 x i8> <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>, align 16 4@llvm_mips_bmnzi_b_ARG2 = global <16 x i8> zeroinitializer, align 16 5@llvm_mips_bmnzi_b_RES = global <16 x i8> zeroinitializer, align 16 6 7define void @llvm_mips_bmnzi_b_test() nounwind { 8entry: 9 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bmnzi_b_ARG1 10 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_bmnzi_b_ARG2 11 %2 = tail call <16 x i8> @llvm.mips.bmnzi.b(<16 x i8> %0, <16 x i8> %1, i32 240) 12 store volatile <16 x i8> %2, <16 x i8>* @llvm_mips_bmnzi_b_RES 13 %3 = tail call <16 x i8> @llvm.mips.bmnzi.b(<16 x i8> %0, <16 x i8> %1, i32 15) 14 store volatile <16 x i8> %3, <16 x i8>* @llvm_mips_bmnzi_b_RES 15 %4 = tail call <16 x i8> @llvm.mips.bmnzi.b(<16 x i8> %0, <16 x i8> %1, i32 170) 16 store <16 x i8> %4, <16 x i8>* @llvm_mips_bmnzi_b_RES 17 ret void 18} 19; CHECK-LABEL: llvm_mips_bmnzi_b_test: 20; CHECK: lw [[R0:\$[0-9]+]], %got(llvm_mips_bmnzi_b_RES)( 21; CHECK: lw [[R1:\$[0-9]+]], %got(llvm_mips_bmnzi_b_ARG1)( 22; CHECK: lw [[R2:\$[0-9]+]], %got(llvm_mips_bmnzi_b_ARG2)( 23; CHECK: ld.b [[R3:\$w[0-9]+]], 0([[R2]]) 24; CHECK: ld.b [[R4:\$w[0-9]+]], 0([[R1]]) 25; CHECK: move.v [[R5:\$w[0-9]+]], [[R4]] 26; CHECK: binsli.b [[R5]], [[R3]], 3 27; CHECK: binsri.b [[R5]], [[R3]], 3 28; CHECK: bmnzi.b [[R4]], [[R3]], 170 29 30define void @llvm_mips_bmzi_b_test() nounwind { 31entry: 32 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bmnzi_b_ARG1 33 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_bmnzi_b_ARG2 34 %2 = tail call <16 x i8> @llvm.mips.bmzi.b(<16 x i8> %0, <16 x i8> %1, i32 240) 35 store volatile <16 x i8> %2, <16 x i8>* @llvm_mips_bmnzi_b_RES 36 %3 = tail call <16 x i8> @llvm.mips.bmzi.b(<16 x i8> %0, <16 x i8> %1, i32 15) 37 store volatile <16 x i8> %3, <16 x i8>* @llvm_mips_bmnzi_b_RES 38 %4 = tail call <16 x i8> @llvm.mips.bmzi.b(<16 x i8> %0, <16 x i8> %1, i32 170) 39 store <16 x i8> %4, <16 x i8>* @llvm_mips_bmnzi_b_RES 40 ret void 41} 42; CHECK-LABEL: llvm_mips_bmzi_b_test: 43; CHECK: lw [[R0:\$[0-9]+]], %got(llvm_mips_bmnzi_b_RES)( 44; CHECK: lw [[R1:\$[0-9]+]], %got(llvm_mips_bmnzi_b_ARG2)( 45; CHECK: lw [[R2:\$[0-9]+]], %got(llvm_mips_bmnzi_b_ARG1)( 46; CHECK: ld.b [[R3:\$w[0-9]+]], 0([[R2]]) 47; CHECK: ld.b [[R4:\$w[0-9]+]], 0([[R1]]) 48; CHECK: move.v [[R5:\$w[0-9]+]], [[R4]] 49; CHECK: binsli.b [[R5]], [[R3]], 3 50; CHECK: binsri.b [[R5]], [[R3]], 3 51; bmnzi.b is the same as bmzi.b with ws and wd_in swapped 52; CHECK: bmnzi.b [[R4]], [[R3]], 170 53 54declare <16 x i8> @llvm.mips.bmnzi.b(<16 x i8>, <16 x i8>, i32) nounwind 55declare <16 x i8> @llvm.mips.bmzi.b(<16 x i8>, <16 x i8>, i32) nounwind 56