• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1; Test the MSA intrinsics that are encoded with the I10 instruction format.
2
3; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
4; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
5
6@llvm_mips_bnz_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
7
8define i32 @llvm_mips_bnz_b_test() nounwind {
9entry:
10  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bnz_b_ARG1
11  %1 = tail call i32 @llvm.mips.bnz.b(<16 x i8> %0)
12  %2 = icmp eq i32 %1, 0
13  br i1 %2, label %true, label %false
14true:
15  ret i32 2
16false:
17  ret i32 3
18}
19
20declare i32 @llvm.mips.bnz.b(<16 x i8>) nounwind
21
22; CHECK: llvm_mips_bnz_b_test:
23; CHECK-DAG: ld.b [[R0:\$w[0-9]+]]
24; CHECK-DAG: bnz.b [[R0]]
25; CHECK: .size llvm_mips_bnz_b_test
26
27@llvm_mips_bnz_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
28
29define i32 @llvm_mips_bnz_h_test() nounwind {
30entry:
31  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_bnz_h_ARG1
32  %1 = tail call i32 @llvm.mips.bnz.h(<8 x i16> %0)
33  %2 = icmp eq i32 %1, 0
34  br i1 %2, label %true, label %false
35true:
36  ret i32 2
37false:
38  ret i32 3
39}
40
41declare i32 @llvm.mips.bnz.h(<8 x i16>) nounwind
42
43; CHECK: llvm_mips_bnz_h_test:
44; CHECK-DAG: ld.h [[R0:\$w[0-9]+]]
45; CHECK-DAG: bnz.h [[R0]]
46; CHECK: .size llvm_mips_bnz_h_test
47
48@llvm_mips_bnz_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
49
50define i32 @llvm_mips_bnz_w_test() nounwind {
51entry:
52  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_bnz_w_ARG1
53  %1 = tail call i32 @llvm.mips.bnz.w(<4 x i32> %0)
54  %2 = icmp eq i32 %1, 0
55  br i1 %2, label %true, label %false
56true:
57  ret i32 2
58false:
59  ret i32 3
60}
61
62declare i32 @llvm.mips.bnz.w(<4 x i32>) nounwind
63
64; CHECK: llvm_mips_bnz_w_test:
65; CHECK-DAG: ld.w [[R0:\$w[0-9]+]]
66; CHECK-DAG: bnz.w [[R0]]
67; CHECK: .size llvm_mips_bnz_w_test
68
69@llvm_mips_bnz_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
70
71define i32 @llvm_mips_bnz_d_test() nounwind {
72entry:
73  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_bnz_d_ARG1
74  %1 = tail call i32 @llvm.mips.bnz.d(<2 x i64> %0)
75  %2 = icmp eq i32 %1, 0
76  br i1 %2, label %true, label %false
77true:
78  ret i32 2
79false:
80  ret i32 3
81}
82
83declare i32 @llvm.mips.bnz.d(<2 x i64>) nounwind
84
85; CHECK: llvm_mips_bnz_d_test:
86; CHECK-DAG: ld.d [[R0:\$w[0-9]+]]
87; CHECK-DAG: bnz.d [[R0]]
88; CHECK: .size llvm_mips_bnz_d_test
89
90@llvm_mips_ldi_b_RES1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
91@llvm_mips_ldi_b_RES2 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
92
93define void @llvm_mips_ldi_b_test() nounwind {
94entry:
95  %0 = call <16 x i8> @llvm.mips.ldi.b(i32 3)
96  store <16 x i8> %0, <16 x i8>* @llvm_mips_ldi_b_RES1
97  %1 = call <16 x i8> @llvm.mips.ldi.b(i32 -3)
98  store <16 x i8> %1, <16 x i8>* @llvm_mips_ldi_b_RES2
99  ret void
100}
101
102declare <16 x i8> @llvm.mips.ldi.b(i32)
103
104; CHECK-LABEL: llvm_mips_ldi_b_test
105; CHECK-DAG: ldi.b {{\$w[0-9]}}, 3
106; CHECK-DAG: ldi.b {{\$w[0-9]}}, -3
107
108@llvm_mips_ldi_h_RES1 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
109@llvm_mips_ldi_h_RES2 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
110
111define void @llvm_mips_ldi_h_test() nounwind {
112entry:
113  %0 = call <8 x i16> @llvm.mips.ldi.h(i32 3)
114  store <8 x i16> %0, <8 x i16>* @llvm_mips_ldi_h_RES1
115  %1 = call <8 x i16> @llvm.mips.ldi.h(i32 -3)
116  store <8 x i16> %1, <8 x i16>* @llvm_mips_ldi_h_RES2
117  ret void
118}
119
120declare <8 x i16> @llvm.mips.ldi.h(i32)
121
122; CHECK-LABEL: llvm_mips_ldi_h_test
123; CHECK-DAG: ldi.h {{\$w[0-9]}}, 3
124; CHECK-DAG: ldi.h {{\$w[0-9]}}, -3
125
126@llvm_mips_ldi_w_RES1 = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
127@llvm_mips_ldi_w_RES2 = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
128
129define void @llvm_mips_ldi_w_test() nounwind {
130entry:
131  %0 = call <4 x i32> @llvm.mips.ldi.w(i32 3)
132  store <4 x i32> %0, <4 x i32>* @llvm_mips_ldi_w_RES1
133  %1 = call <4 x i32> @llvm.mips.ldi.w(i32 -3)
134  store <4 x i32> %1, <4 x i32>* @llvm_mips_ldi_w_RES2
135  ret void
136}
137
138declare <4 x i32> @llvm.mips.ldi.w(i32)
139
140; CHECK-LABEL: llvm_mips_ldi_w_test
141; CHECK-DAG: ldi.w {{\$w[0-9]}}, 3
142; CHECK-DAG: ldi.w {{\$w[0-9]}}, -3
143
144@llvm_mips_ldi_d_RES1 = global <2 x i64> <i64 0, i64 0>, align 16
145@llvm_mips_ldi_d_RES2 = global <2 x i64> <i64 0, i64 0>, align 16
146
147define void @llvm_mips_ldi_d_test() nounwind {
148entry:
149  %0 = call <2 x i64> @llvm.mips.ldi.d(i32 3)
150  store <2 x i64> %0, <2 x i64>* @llvm_mips_ldi_d_RES1
151  %1 = call <2 x i64> @llvm.mips.ldi.d(i32 -3)
152  store <2 x i64> %1, <2 x i64>* @llvm_mips_ldi_d_RES2
153  ret void
154}
155
156declare <2 x i64> @llvm.mips.ldi.d(i32)
157
158; CHECK-LABEL: llvm_mips_ldi_d_test
159; CHECK-DAG: ldi.d {{\$w[0-9]}}, 3
160; CHECK-DAG: ldi.d {{\$w[0-9]}}, -3
161