1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \ 3; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names \ 4; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s 5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \ 6; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names \ 7; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE 8 9; Test reduce scalarization in fpext v2f32 to v2f64 from the extract_subvector v4f32 node. 10 11define dso_local void @test(<4 x float>* nocapture readonly %a, <2 x double>* nocapture %b, <2 x double>* nocapture %c) { 12; CHECK-LABEL: test: 13; CHECK: # %bb.0: # %entry 14; CHECK-NEXT: lxv vs0, 0(r3) 15; CHECK-NEXT: xxmrglw vs1, vs0, vs0 16; CHECK-NEXT: xxmrghw vs0, vs0, vs0 17; CHECK-NEXT: xvcvspdp vs1, vs1 18; CHECK-NEXT: xvcvspdp vs0, vs0 19; CHECK-NEXT: stxv vs1, 0(r4) 20; CHECK-NEXT: stxv vs0, 0(r5) 21; CHECK-NEXT: blr 22; 23; CHECK-BE-LABEL: test: 24; CHECK-BE: # %bb.0: # %entry 25; CHECK-BE-NEXT: lxv vs0, 0(r3) 26; CHECK-BE-NEXT: xxmrghw vs1, vs0, vs0 27; CHECK-BE-NEXT: xxmrglw vs0, vs0, vs0 28; CHECK-BE-NEXT: xvcvspdp vs1, vs1 29; CHECK-BE-NEXT: xvcvspdp vs0, vs0 30; CHECK-BE-NEXT: stxv vs1, 0(r4) 31; CHECK-BE-NEXT: stxv vs0, 0(r5) 32; CHECK-BE-NEXT: blr 33entry: 34 %0 = load <4 x float>, <4 x float>* %a, align 16 35 %shuffle = shufflevector <4 x float> %0, <4 x float> undef, <2 x i32> <i32 0, i32 1> 36 %shuffle1 = shufflevector <4 x float> %0, <4 x float> undef, <2 x i32> <i32 2, i32 3> 37 %vecinit4 = fpext <2 x float> %shuffle to <2 x double> 38 %vecinit11 = fpext <2 x float> %shuffle1 to <2 x double> 39 store <2 x double> %vecinit4, <2 x double>* %b, align 16 40 store <2 x double> %vecinit11, <2 x double>* %c, align 16 41 ret void 42} 43 44; Ensure we don't crash for wider types 45 46define dso_local void @test2(<16 x float>* nocapture readonly %a, <2 x double>* nocapture %b, <2 x double>* nocapture %c) { 47; CHECK-LABEL: test2: 48; CHECK: # %bb.0: # %entry 49; CHECK-NEXT: lxv vs0, 0(r3) 50; CHECK-NEXT: xxmrglw vs1, vs0, vs0 51; CHECK-NEXT: xxmrghw vs0, vs0, vs0 52; CHECK-NEXT: xvcvspdp vs1, vs1 53; CHECK-NEXT: xvcvspdp vs0, vs0 54; CHECK-NEXT: stxv vs1, 0(r4) 55; CHECK-NEXT: stxv vs0, 0(r5) 56; CHECK-NEXT: blr 57; 58; CHECK-BE-LABEL: test2: 59; CHECK-BE: # %bb.0: # %entry 60; CHECK-BE-NEXT: lxv vs0, 0(r3) 61; CHECK-BE-NEXT: xxmrghw vs1, vs0, vs0 62; CHECK-BE-NEXT: xxmrglw vs0, vs0, vs0 63; CHECK-BE-NEXT: xvcvspdp vs1, vs1 64; CHECK-BE-NEXT: xvcvspdp vs0, vs0 65; CHECK-BE-NEXT: stxv vs1, 0(r4) 66; CHECK-BE-NEXT: stxv vs0, 0(r5) 67; CHECK-BE-NEXT: blr 68entry: 69 %0 = load <16 x float>, <16 x float>* %a, align 16 70 %shuffle = shufflevector <16 x float> %0, <16 x float> undef, <2 x i32> <i32 0, i32 1> 71 %shuffle1 = shufflevector <16 x float> %0, <16 x float> undef, <2 x i32> <i32 2, i32 3> 72 %vecinit4 = fpext <2 x float> %shuffle to <2 x double> 73 %vecinit11 = fpext <2 x float> %shuffle1 to <2 x double> 74 store <2 x double> %vecinit4, <2 x double>* %b, align 16 75 store <2 x double> %vecinit11, <2 x double>* %c, align 16 76 ret void 77} 78