1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ 3; RUN: | FileCheck -check-prefix=RV32I %s 4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ 5; RUN: | FileCheck -check-prefix=RV64I %s 6 7; These test that constant adds are not moved after shifts by DAGCombine, 8; if the constant is cheaper to materialise before it has been shifted. 9 10define signext i32 @add_small_const(i32 signext %a) nounwind { 11; RV32I-LABEL: add_small_const: 12; RV32I: # %bb.0: 13; RV32I-NEXT: addi a0, a0, 1 14; RV32I-NEXT: slli a0, a0, 24 15; RV32I-NEXT: srai a0, a0, 24 16; RV32I-NEXT: ret 17; 18; RV64I-LABEL: add_small_const: 19; RV64I: # %bb.0: 20; RV64I-NEXT: addi a0, a0, 1 21; RV64I-NEXT: slli a0, a0, 56 22; RV64I-NEXT: srai a0, a0, 56 23; RV64I-NEXT: ret 24 %1 = add i32 %a, 1 25 %2 = shl i32 %1, 24 26 %3 = ashr i32 %2, 24 27 ret i32 %3 28} 29 30define signext i32 @add_large_const(i32 signext %a) nounwind { 31; RV32I-LABEL: add_large_const: 32; RV32I: # %bb.0: 33; RV32I-NEXT: slli a0, a0, 16 34; RV32I-NEXT: lui a1, 65520 35; RV32I-NEXT: add a0, a0, a1 36; RV32I-NEXT: srai a0, a0, 16 37; RV32I-NEXT: ret 38; 39; RV64I-LABEL: add_large_const: 40; RV64I: # %bb.0: 41; RV64I-NEXT: lui a1, 1 42; RV64I-NEXT: addiw a1, a1, -1 43; RV64I-NEXT: add a0, a0, a1 44; RV64I-NEXT: slli a0, a0, 48 45; RV64I-NEXT: srai a0, a0, 48 46; RV64I-NEXT: ret 47 %1 = add i32 %a, 4095 48 %2 = shl i32 %1, 16 49 %3 = ashr i32 %2, 16 50 ret i32 %3 51} 52 53define signext i32 @add_huge_const(i32 signext %a) nounwind { 54; RV32I-LABEL: add_huge_const: 55; RV32I: # %bb.0: 56; RV32I-NEXT: slli a0, a0, 16 57; RV32I-NEXT: lui a1, 524272 58; RV32I-NEXT: add a0, a0, a1 59; RV32I-NEXT: srai a0, a0, 16 60; RV32I-NEXT: ret 61; 62; RV64I-LABEL: add_huge_const: 63; RV64I: # %bb.0: 64; RV64I-NEXT: lui a1, 8 65; RV64I-NEXT: addiw a1, a1, -1 66; RV64I-NEXT: add a0, a0, a1 67; RV64I-NEXT: slli a0, a0, 48 68; RV64I-NEXT: srai a0, a0, 48 69; RV64I-NEXT: ret 70 %1 = add i32 %a, 32767 71 %2 = shl i32 %1, 16 72 %3 = ashr i32 %2, 16 73 ret i32 %3 74} 75 76define signext i24 @add_non_machine_type(i24 signext %a) nounwind { 77; RV32I-LABEL: add_non_machine_type: 78; RV32I: # %bb.0: 79; RV32I-NEXT: addi a0, a0, 256 80; RV32I-NEXT: slli a0, a0, 20 81; RV32I-NEXT: srai a0, a0, 8 82; RV32I-NEXT: ret 83; 84; RV64I-LABEL: add_non_machine_type: 85; RV64I: # %bb.0: 86; RV64I-NEXT: addi a0, a0, 256 87; RV64I-NEXT: slli a0, a0, 52 88; RV64I-NEXT: srai a0, a0, 40 89; RV64I-NEXT: ret 90 %1 = add i24 %a, 256 91 %2 = shl i24 %1, 12 92 ret i24 %2 93} 94 95define i128 @add_wide_operand(i128 %a) nounwind { 96; RV32I-LABEL: add_wide_operand: 97; RV32I: # %bb.0: 98; RV32I-NEXT: lw a2, 0(a1) 99; RV32I-NEXT: lw a3, 4(a1) 100; RV32I-NEXT: lw a6, 12(a1) 101; RV32I-NEXT: lw a1, 8(a1) 102; RV32I-NEXT: srli a5, a2, 29 103; RV32I-NEXT: slli a4, a3, 3 104; RV32I-NEXT: or a4, a4, a5 105; RV32I-NEXT: srli a3, a3, 29 106; RV32I-NEXT: slli a5, a1, 3 107; RV32I-NEXT: or a3, a5, a3 108; RV32I-NEXT: srli a1, a1, 29 109; RV32I-NEXT: slli a5, a6, 3 110; RV32I-NEXT: or a1, a5, a1 111; RV32I-NEXT: slli a2, a2, 3 112; RV32I-NEXT: lui a5, 128 113; RV32I-NEXT: add a1, a1, a5 114; RV32I-NEXT: sw a2, 0(a0) 115; RV32I-NEXT: sw a3, 8(a0) 116; RV32I-NEXT: sw a4, 4(a0) 117; RV32I-NEXT: sw a1, 12(a0) 118; RV32I-NEXT: ret 119; 120; RV64I-LABEL: add_wide_operand: 121; RV64I: # %bb.0: 122; RV64I-NEXT: srli a2, a0, 61 123; RV64I-NEXT: slli a1, a1, 3 124; RV64I-NEXT: or a1, a1, a2 125; RV64I-NEXT: slli a0, a0, 3 126; RV64I-NEXT: addi a2, zero, 1 127; RV64I-NEXT: slli a2, a2, 51 128; RV64I-NEXT: add a1, a1, a2 129; RV64I-NEXT: ret 130 %1 = add i128 %a, 5192296858534827628530496329220096 131 %2 = shl i128 %1, 3 132 ret i128 %2 133} 134